xref: /rk3399_rockchip-uboot/arch/arm/cpu/armv8/sec_firmware_asm.S (revision 0675f992dbf4a785a05a1baf149c2bce6aa5fe90)
1b45db3b5SHou Zhiqiang/*
2b45db3b5SHou Zhiqiang * Copyright 2016 NXP Semiconductor, Inc.
3b45db3b5SHou Zhiqiang *
4b45db3b5SHou Zhiqiang * SPDX-License-Identifier:	GPL-2.0+
5b45db3b5SHou Zhiqiang */
6b45db3b5SHou Zhiqiang
7b45db3b5SHou Zhiqiang#include <config.h>
8b45db3b5SHou Zhiqiang#include <linux/linkage.h>
9b45db3b5SHou Zhiqiang#include <asm/system.h>
10b45db3b5SHou Zhiqiang#include <asm/macro.h>
11b45db3b5SHou Zhiqiang
12b45db3b5SHou ZhiqiangWEAK(_sec_firmware_entry)
13b45db3b5SHou Zhiqiang	/*
14b45db3b5SHou Zhiqiang	 * x0: Secure Firmware entry point
15b45db3b5SHou Zhiqiang	 * x1: Exception return address Low
16b45db3b5SHou Zhiqiang	 * x2: Exception return address High
17b45db3b5SHou Zhiqiang	 */
18b45db3b5SHou Zhiqiang
19b45db3b5SHou Zhiqiang	/* Save stack pointer for EL2 */
20b45db3b5SHou Zhiqiang	mov	x3, sp
21b45db3b5SHou Zhiqiang	msr	sp_el2, x3
22b45db3b5SHou Zhiqiang
23b45db3b5SHou Zhiqiang	/* Set exception return address hold pointer */
24b45db3b5SHou Zhiqiang        adr	x4, 1f
25b45db3b5SHou Zhiqiang        mov	x3, x4
260897eb2cSHou Zhiqiang#ifdef CONFIG_ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
27b45db3b5SHou Zhiqiang        rev	w3, w3
28b45db3b5SHou Zhiqiang#endif
29b45db3b5SHou Zhiqiang        str	w3, [x1]
30b45db3b5SHou Zhiqiang        lsr	x3, x4, #32
310897eb2cSHou Zhiqiang#ifdef CONFIG_ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
32b45db3b5SHou Zhiqiang        rev	w3, w3
33b45db3b5SHou Zhiqiang#endif
34b45db3b5SHou Zhiqiang        str	w3, [x2]
35b45db3b5SHou Zhiqiang
36b45db3b5SHou Zhiqiang	/* Call SEC monitor */
37b45db3b5SHou Zhiqiang        br	x0
38b45db3b5SHou Zhiqiang
39b45db3b5SHou Zhiqiang1:
40b45db3b5SHou Zhiqiang        mov	x0, #0
41b45db3b5SHou Zhiqiang        ret
42b45db3b5SHou ZhiqiangENDPROC(_sec_firmware_entry)
43b45db3b5SHou Zhiqiang
44*daa92644SHou Zhiqiang#ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI
45b45db3b5SHou ZhiqiangENTRY(_sec_firmware_support_psci_version)
46b45db3b5SHou Zhiqiang	mov	x0, 0x84000000
47b45db3b5SHou Zhiqiang	mov	x1, 0x0
48b45db3b5SHou Zhiqiang	mov	x2, 0x0
49b45db3b5SHou Zhiqiang	mov	x3, 0x0
50b45db3b5SHou Zhiqiang	smc	#0
51b45db3b5SHou Zhiqiang	ret
52b45db3b5SHou ZhiqiangENDPROC(_sec_firmware_support_psci_version)
533db86f4bSAlison Wang
543db86f4bSAlison Wang/*
553db86f4bSAlison Wang * Switch from AArch64 EL2 to AArch32 EL2
563db86f4bSAlison Wang * @param inputs:
573db86f4bSAlison Wang * x0: argument, zero
583db86f4bSAlison Wang * x1: machine nr
593db86f4bSAlison Wang * x2: fdt address
607c5e1febSAlison Wang * x3: input argument
617c5e1febSAlison Wang * x4: kernel entry point
623db86f4bSAlison Wang * @param outputs for secure firmware:
633db86f4bSAlison Wang * x0: function id
643db86f4bSAlison Wang * x1: kernel entry point
653db86f4bSAlison Wang * x2: machine nr
663db86f4bSAlison Wang * x3: fdt address
673db86f4bSAlison Wang*/
683db86f4bSAlison WangENTRY(armv8_el2_to_aarch32)
693db86f4bSAlison Wang	mov	x3, x2
703db86f4bSAlison Wang	mov	x2, x1
717c5e1febSAlison Wang	mov	x1, x4
723db86f4bSAlison Wang	ldr	x0, =0xc000ff04
733db86f4bSAlison Wang	smc	#0
743db86f4bSAlison Wang	ret
753db86f4bSAlison WangENDPROC(armv8_el2_to_aarch32)
76b45db3b5SHou Zhiqiang#endif
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