109f455dcSMasahiro Yamada/* 209f455dcSMasahiro Yamada * SoC-specific setup info 309f455dcSMasahiro Yamada * 409f455dcSMasahiro Yamada * (C) Copyright 2010,2011 509f455dcSMasahiro Yamada * NVIDIA Corporation <www.nvidia.com> 609f455dcSMasahiro Yamada * 709f455dcSMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 809f455dcSMasahiro Yamada */ 909f455dcSMasahiro Yamada 1009f455dcSMasahiro Yamada#include <config.h> 1109f455dcSMasahiro Yamada#include <linux/linkage.h> 1209f455dcSMasahiro Yamada 13*7aaa5a60STom Warren#ifdef CONFIG_ARM64 14*7aaa5a60STom Warren .align 5 15*7aaa5a60STom WarrenENTRY(reset_cpu) 16*7aaa5a60STom Warren /* get address for global reset register */ 17*7aaa5a60STom Warren ldr x1, =PRM_RSTCTRL 18*7aaa5a60STom Warren ldr w3, [x1] 19*7aaa5a60STom Warren /* force reset */ 20*7aaa5a60STom Warren orr w3, w3, #0x10 21*7aaa5a60STom Warren str w3, [x1] 22*7aaa5a60STom Warren mov w0, w0 23*7aaa5a60STom Warren1: 24*7aaa5a60STom Warren b 1b 25*7aaa5a60STom WarrenENDPROC(reset_cpu) 26*7aaa5a60STom Warren#else 2709f455dcSMasahiro Yamada .align 5 2809f455dcSMasahiro YamadaENTRY(reset_cpu) 2909f455dcSMasahiro Yamada ldr r1, rstctl @ get addr for global reset 3009f455dcSMasahiro Yamada @ reg 3109f455dcSMasahiro Yamada ldr r3, [r1] 3209f455dcSMasahiro Yamada orr r3, r3, #0x10 3309f455dcSMasahiro Yamada str r3, [r1] @ force reset 3409f455dcSMasahiro Yamada mov r0, r0 3509f455dcSMasahiro Yamada_loop_forever: 3609f455dcSMasahiro Yamada b _loop_forever 3709f455dcSMasahiro Yamadarstctl: 3809f455dcSMasahiro Yamada .word PRM_RSTCTRL 3909f455dcSMasahiro YamadaENDPROC(reset_cpu) 40*7aaa5a60STom Warren#endif 41