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/rk3399_rockchip-uboot/arch/arm/dts/
H A Dsama5d3_gmac.dtsi2 * sama5d3_gmac.dtsi - Device Tree Include file for SAMA5D3 SoC with
20 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
21 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
22 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
23 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
24 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
25 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
26 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
27 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
31 … <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */
[all …]
H A Dat91sam9x5_isi.dtsi2 * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
20 <AT91_PIOC 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D0, conflicts with LCDDAT0 */
21 AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D1, conflicts with LCDDAT1 */
22 AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D2, conflicts with LCDDAT2 */
23 AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D3, conflicts with LCDDAT3 */
24 AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D4, conflicts with LCDDAT4 */
25 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D5, conflicts with LCDDAT5 */
26 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D6, conflicts with LCDDAT6 */
27 AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D7, conflicts with LCDDAT7 */
28 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_PCK, conflicts with LCDDAT12 */
[all …]
H A Dsama5d3_mci2.dtsi2 * sama5d3_mci2.dtsi - Device Tree Include file for SAMA5D3 SoC with
21 … <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
22 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
23 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
27 …2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
28 …3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
29 …AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
H A Dsama5d3_emac.dtsi2 * sama5d3_emac.dtsi - Device Tree Include file for SAMA5D3 SoC with
20 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */
21 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */
22 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */
23 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */
24 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */
25 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */
26 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */
27 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */
28 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */
H A Dsama5d3.dtsi554 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
558 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
568 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
575 …<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI…
576 …AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, I…
583 …<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1…
584 …AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPC…
591 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
592 … AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
599 … <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
[all …]
H A Dsama5d3_uart.dtsi2 * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with
26 … <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
27 …_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK…
34 … <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
35 …_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, …
H A Dat91sam9x5_can.dtsi2 * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
56 <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0, conflicts with DRXD */
57 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX0, conflicts with DTXD */
64 <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1, conflicts with RXD1 */
65 AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX1, conflicts with TXD1 */
H A Dsama5d3_can.dtsi2 * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with
20 …<AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1…
21 …AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS…
28 <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
29 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
/rk3399_rockchip-uboot/arch/microblaze/include/asm/
H A Dsystem.h130 #define xchg(ptr, with) \ argument
131 ((__typeof__ (*(ptr)))__xchg ((unsigned long)(with), (ptr), sizeof (*(ptr))))
134 static inline unsigned long __xchg(unsigned long with, in __xchg() argument
144 *(unsigned char *)ptr = with; in __xchg()
148 *(unsigned short *)ptr = with; in __xchg()
152 *(unsigned long *)ptr = with; in __xchg()
/rk3399_rockchip-uboot/arch/mips/mach-bmips/
H A DKconfig92 Comtrend AR-5387un boards have a BCM6328 SoC with 64 MB of RAM and 16
94 Between its different peripherals there's an integrated switch with 4
103 Comtrend CT-5361 boards have a BCM6348 SoC with 16 MB of RAM and 4 MB
105 Between its different peripherals there's a BCM5325 switch with 4
114 Comtrend VR-3032u boards have a BCM63268 SoC with 64 MB of RAM and
116 Between its different peripherals there's an integrated switch with 4
125 Huawei EchoLife HG556a boards have a BCM6358 SoC with 64 MB of RAM
127 Between its different peripherals there's a BCM5325 switch with 4
136 Netgear CG3100D boards have a BCM3380 SoC with 64 MB of RAM and 8 MB
138 Between its different peripherals there's a BCM53115 switch with 4
[all …]
/rk3399_rockchip-uboot/arch/x86/dts/
H A Du-boot.dtsi27 u-boot-spl-with-ucode-ptr {
31 u-boot-dtb-with-ucode2 {
32 type = "u-boot-dtb-with-ucode";
38 u-boot-with-ucode-ptr {
42 u-boot-dtb-with-ucode {
/rk3399_rockchip-uboot/board/freescale/bsc9131rdb/
H A DREADME5 technologies with MAPLE-B2F baseband acceleration processing elements.
9 . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
11 . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
20 . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
24 . OCNDMA with four bidirectional channels
30 . High-speed USB 2.0 host and device controller with ULPI interface
38 . TDM with one TDM port
41 . TDM with 256 channels
92 1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
94 2. NAND Flash with sysclk 100MHz(J16 on RDB open)
[all …]
/rk3399_rockchip-uboot/board/freescale/mx35pdk/
H A DREADME6 - CPU module, with CPU, RAM, flash
7 - Personality board, with most interfaces (USB, Network,..)
8 - Debug board with JTAG header.
10 The board is usually delivered with redboot. This howto explains how to boot
11 a linux kernel and how to replace the original bootloader with U-Boot.
13 The board is delivered with Redboot on the NAND flash. It is possible to
14 switch the boot device with the switches SW1-SW2 on the Personality board,
15 and with SW5-SW10 on the Debug board.
35 If the ip address is not set, you can set it with :
42 As default, the board is shipped with these partition tables for NAND
[all …]
/rk3399_rockchip-uboot/doc/
H A DREADME.JFFS25 Linux with the same name. To use JFFS2 define CONFIG_CMD_JFFS2.
14 with CONFIG_FS_JFFS2 and call the jffs2 functions yourself.
19 the JFFS2 filesystem takes *much* longer with this feature, though.
27 and you can change where the partition is with two defines.
39 into the disk. The current code do not work with memory holes
40 or hardware with a sliding window (PCMCIA).
H A DREADME.hwconfig11 interface for AMI GUI[1] BIOS-like interface with mouse
21 with the environment directly, there is no way to tell that
26 3. We support hwconfig options with arguments. For example,
33 3. dr_usb_phy_type:ulpi - USB should work with ULPI PHYs.
38 command with bells and whistles. Or not adding, if we feel
42 [2] Regarding ncurses and GUI with mouse support -- I'm just
/rk3399_rockchip-uboot/doc/uImage.FIT/
H A Dcommand_syntax_extensions.txt55 kernel and a ramdisk, respectively. The kernel is booted with initrd loaded
56 with the ramdisk from the image.
58 U-Boot is compiled with OF support:
70 Ad. 5. Boot kernel image located at <addr1> with initrd loaded with ramdisk
76 booted with initrd loaded with ramdisk from the image at <addr2>.
97 at <addr1> with initrd loaded with ramdisk <subimg2> from the image at
102 at <addr1> with initrd loaded with ramdisk <subimg2> from the image at
123 New uImage support introduces two new forms for bootm arguments, with the
132 - new uImage configuration specification with extra configuration components
147 - boot configuration "cfg@1" with extra "cfg@2" from a new uImage located
[all …]
/rk3399_rockchip-uboot/board/phytec/pcm058/
H A DREADME5 The SOM is sold in two versions, with eMMC or with NAND. Support
6 here is for the SOM with NAND.
8 together with the SOM.
31 The bootloader was tested with DIP-1 set to on. If a SD-card
/rk3399_rockchip-uboot/board/keymile/scripts/
H A DREADME14 This file defines variables for working with rootfs via nfs for powerpc and
19 This file defines architecture specific variables for working with rootfs via
25 This file defines variables for working with rootfs inside the ram for powerpc
30 This file defines architecture specific variables for working with rootfs inside
/rk3399_rockchip-uboot/board/advantech/
H A DKconfig10 Advantech SOM-DB5800 COM Express development board with SOM-6867
13 SOM-6867 is a COM Express Type 6 Compact Module with either an Intel
16 SOM-DB5800 is a COM Express Development board with:
/rk3399_rockchip-uboot/lib/efi/
H A DKconfig8 application, with U-Boot using EFI's drivers instead of its own.
34 use. U-Boot allocates this from EFI on start-up (along with a few
36 It is used as the RAM size in with U-Boot.
43 significant problem because it means that you must build a stub with
49 bool "Produce a stub for running with 32-bit EFI"
52 bool "Produce a stub for running with 64-bit EFI"
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 processor cores with datapath acceleration optimized for L2/3 packet
20 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
39 - Three high-speed USB 3.0 controllers with integrated PHY
51 processor cores with high-performance data path acceleration logic and network
58 - 1 MB platform cache with ECC
59 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
80 - Two high-speed USB 3.0 controllers with integrated PHY
95 A53 processor, with 32 KB of parity protected L1-I cache,
100 - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
114 - One USB 3.0/2.0 controller with integrated PHY
[all …]
/rk3399_rockchip-uboot/board/solidrun/clearfog/
H A DREADME4 Generate the U-Boot image with these commands:
9 The resulting image including the SPL binary with the
13 For example with this command:
/rk3399_rockchip-uboot/board/birdland/bav335x/
H A DREADME11 The binary produced supports the bav335x Rev.A with 10/100 MB PHY
12 and Rev.B (default) with GB ethernet PHY.
22 - I2C, to talk with the PMIC and ensure that we do not run afoul of
29 note that all of the SPL options are grouped together, rather than with
/rk3399_rockchip-uboot/drivers/scsi/
H A DKconfig5 a parallel interface widely used with storage peripherals such as
11 bool "Support SCSI controllers with driver model"
16 (IDs/LUNs) a block device is created with RAW read/write and
/rk3399_rockchip-uboot/doc/SPI/
H A DREADME.dual-flash8 to a given controller with single chip select line, but there are some
10 connected with a single chip select line from a controller.
17 - single spi flash memory connected with single chip select line.
28 - dual spi/qspi flash memories are connected with a single chipselect
29 line and these two memories are operating stacked fasion with shared buses.
58 - dual spi/qspi flash memories are connected with a single chipselect
59 line and these two memories are operating parallel with separate buses.

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