Lines Matching refs:with

13 processor cores with datapath acceleration optimized for L2/3 packet
20  - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
39    - Three high-speed USB 3.0 controllers with integrated PHY
51 processor cores with high-performance data path acceleration logic and network
58  - 1 MB platform cache with ECC
59  - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
80    - Two high-speed USB 3.0 controllers with integrated PHY
95 A53 processor, with 32 KB of parity protected L1-I cache,
100  - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
114      - One USB 3.0/2.0 controller with integrated PHY
115      - One USB 2.0 controller with ULPI interface. .
129     - Thermal monitor unit (TMU) with +/- 3C accuracy
137 processor cores with datapath acceleration optimized for L2/3 packet
144  - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
166    - Three high-speed USB 3.0 controllers with integrated PHY
178 processor cores with high-performance data path acceleration logic and network
185  - 1 MB platform cache with ECC
186  - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
207    - Two high-speed USB 3.0 controllers with integrated PHY