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/rk3399_rockchip-uboot/board/freescale/mx6sllevk/
H A Dplugin.S11 ldr r0, =IOMUXC_BASE_ADDR
13 str r1, [r0, #0x550]
15 str r1, [r0, #0x534]
17 str r1, [r0, #0x2AC]
18 str r1, [r0, #0x548]
19 str r1, [r0, #0x52C]
21 str r1, [r0, #0x530]
23 str r1, [r0, #0x2B0]
24 str r1, [r0, #0x2B4]
25 str r1, [r0, #0x2B8]
[all …]
/rk3399_rockchip-uboot/board/freescale/mx31ads/
H A Dlowlevel_init.S36 ldr r0, =0x43F00000
38 str r1, [r0, #0x00]
39 str r1, [r0, #0x04]
40 ldr r0, =0x53F00000
41 str r1, [r0, #0x00]
42 str r1, [r0, #0x04]
49 ldr r0, =0x43F00000
51 str r1, [r0, #0x40]
52 str r1, [r0, #0x44]
53 str r1, [r0, #0x48]
[all …]
/rk3399_rockchip-uboot/board/freescale/mx6ullevk/
H A Dplugin.S11 ldr r0, =IOMUXC_BASE_ADDR
13 str r1, [r0, #0x4B4]
15 str r1, [r0, #0x4AC]
17 str r1, [r0, #0x27C]
19 str r1, [r0, #0x250]
20 str r1, [r0, #0x24C]
21 str r1, [r0, #0x490]
23 str r1, [r0, #0x288]
26 str r1, [r0, #0x270]
29 str r1, [r0, #0x260]
[all …]
/rk3399_rockchip-uboot/board/samsung/goni/
H A Dlowlevel_init.S35 ldr r0, [r2]
37 and r0, r0, r1
38 cmp r0, r5
46 ldr r0, =S5PC110_RST_STAT
47 ldr r1, [r0]
54 addeq r0, r8, #0x280 @ S5PC100_GPIO_J4
55 addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4
56 ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
59 str r1, [r0, #0x0] @ GPIO_CON_OFFSET
61 ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx5/
H A Dlowlevel_init.S28 mrc 15, 0, r0, c1, c0, 1
29 bic r0, r0, #0x2
30 mcr 15, 0, r0, c1, c0, 1
33 ldr r0, =0xC0 | /* tag RAM */ \
44 orrls r0, r0, #1 << 25
47 mcr 15, 1, r0, c9, c0, 2
50 mrc 15, 0, r0, c1, c0, 1
51 orr r0, r0, #2
52 mcr 15, 0, r0, c1, c0, 1
63 ldr r0, =AIPS1_BASE_ADDR
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/pxa/
H A Dstart.S44 mrs r0,cpsr
45 bic r0,r0,#0x1f
46 orr r0,r0,#0xd3
47 msr cpsr,r0
60 ldr r0,=CKEN
61 ldr r1,[r0]
63 str r1,[r0]
101 mov r0, #0
102 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
103 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
[all …]
/rk3399_rockchip-uboot/arch/arc/lib/
H A Dstrcmp.S19 or %r2, %r0, %r1
25 ld.ab %r2, [%r0, 4]
34 xor %r0, %r2, %r3 /* mask for difference */
35 sub_s %r1, %r0, 1
36 bic_s %r0, %r0, %r1 /* mask for least significant difference bit */
37 sub %r1, %r5, %r0
38 xor %r0, %r5, %r1 /* mask for least significant difference byte */
39 and_s %r2, %r2, %r0
40 and_s %r3, %r3, %r0
43 mov_s %r0, 1
[all …]
/rk3399_rockchip-uboot/board/freescale/mx7ulp_evk/
H A Dplugin.S68 ldr r0, =0x40ad0000
70 str r1, [r0, #0x128]
72 str r1, [r0, #0xf8]
74 str r1, [r0, #0xd8]
76 str r1, [r0, #0x108]
78 str r1, [r0, #0x104]
80 str r1, [r0, #0x124]
82 str r1, [r0, #0x80]
84 str r1, [r0, #0x84]
86 str r1, [r0, #0x88]
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm920t/ep93xx/
H A Dlowlevel_init.S32 str r0, [r3, #SDRAM_OFF_DEVCFG0]
35 str r0, [r3, #SDRAM_OFF_DEVCFG1]
38 str r0, [r3, #SDRAM_OFF_DEVCFG2]
41 str r0, [r3, #SDRAM_OFF_DEVCFG3]
111 stmia r0, {r1-r4}
116 ldr r5, [r0]
118 ldreq r5, [r0, #0x0004]
120 ldreq r5, [r0, #0x0008]
122 ldreq r5, [r0, #0x000c]
126 mvnne r0, #0xffffffff
[all …]
/rk3399_rockchip-uboot/arch/sh/lib/
H A Dashrsi3.S30 ! r0: Result
41 mov #31,r0
42 and r0,r5
43 mova ashrsi3_table,r0
44 mov.b @(r0,r5),r5
46 add r5,r0
47 jmp @r0
51 mov r4,r0
89 rotcl r0
91 subc r0,r0
[all …]
H A Dashlsi3.S30 ! r0: Result
39 mov #31,r0
40 and r0,r5
41 mova __ashlsi3_table,r0
42 mov.b @(r0,r5),r5
44 add r5,r0
45 jmp @r0
49 mov r4,r0
87 shll2 r0
89 shll2 r0
[all …]
H A Dlshrsi3.S30 ! r0: Result
39 mov #31,r0
40 and r0,r5
41 mova __lshrsi3_table,r0
42 mov.b @(r0,r5),r5
44 add r5,r0
45 jmp @r0
49 mov r4,r0
87 shlr2 r0
89 shlr2 r0
[all …]
H A Dudivsi3_i4i.S44 mov r4,r0
45 shlr8 r0
51 shlr r0
55 div1 r5,r0
57 div1 r5,r0
58 div1 r5,r0
60 div1 r5,r0
63 mova div_table_ix,r0
65 mov.b @(r0,r5),r1
68 mova div_table_ix,r0
[all …]
/rk3399_rockchip-uboot/arch/microblaze/cpu/
H A Dstart.S24 mts rmsr, r0 /* disable cache */
26 addi r8, r0, __end
30 addi r1, r0, CONFIG_SPL_STACK_ADDR
35 addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_VAL(SYS_MALLOC_F_LEN)
37 addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
51 addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
52 lwi r7, r0, 0x28
53 swi r6, r0, 0x28 /* used first unused MB vector */
54 lbui r10, r0, 0x28 /* used first unused MB vector */
55 swi r7, r0, 0x28
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/
H A Dstart.S49 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
50 and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
51 cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
59 mrs r0, cpsr
60 and r1, r0, #0x1f @ mask mode bits
62 bicne r0, r0, #0x1f @ clear all mode bits
63 orrne r0, r0, #0x13 @ set SVC mode
64 orr r0, r0, #0xc0 @ disable FIQ and IRQ
65 msr cpsr,r0
68 mrc p15, 0, r0, c1, c0, 1
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/arm32/
H A Ddebug_ll.S24 ldr r0, =SG_REVISION
25 ldr r1, [r0]
34 ldr r0, =SG_IECTRL
35 ldr r1, [r0]
37 str r1, [r0]
39 sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0
51 sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
53 ldr r0, =SG_LOADPINCTRL
55 str r1, [r0]
57 ldr r0, =SC_CLKCTRL
[all …]
H A Dlowlevel_init.S24 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
25 orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
26 mcr p15, 0, r0, c1, c0, 0
43 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
44 bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
45 mcr p15, 0, r0, c1, c0, 0
54 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
55 bic r0, r0, #0x37
56 orr r0, r0, #0x20 @ disable TTBR1
57 mcr p15, 0, r0, c2, c0, 2
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/
H A Dstart.S41 mrs r0,cpsr
42 bic r0,r0,#0x1f
43 orr r0,r0,#0xd3
44 msr cpsr,r0
78 mov r0, #0
83 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
84 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
90 mrc p15, 0, r0, c1, c0, 0
91 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
92 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
[all …]
/rk3399_rockchip-uboot/post/lib_powerpc/
H A Dasm.S20 mflr r0
21 stwu r0, -4(r1)
34 lwz r0, 0(r1)
36 mtlr r0
43 mflr r0
44 stwu r0, -4(r1)
59 lwz r0, 0(r1)
61 mtlr r0
68 mflr r0
69 stwu r0, -4(r1)
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx35/
H A Dlowlevel_macro.S24 ldr r0, =AIPS1_BASE_ADDR
26 str r1, [r0, #AIPS_MPR_0_7]
27 str r1, [r0, #AIPS_MPR_8_15]
34 str r1, [r0, #AIPS_OPACR_0_7]
35 str r1, [r0, #AIPS_OPACR_8_15]
36 str r1, [r0, #AIPS_OPACR_16_23]
37 str r1, [r0, #AIPS_OPACR_24_31]
38 str r1, [r0, #AIPS_OPACR_32_39]
55 ldr r0, =MAX_BASE_ADDR
57 str r1, [r0, #MAX_MPR0] /* for S0 */
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-rmobile/
H A Dlowlevel_init_ca15.S28 1: ldr r0, [r1, #0x20] /* sbar */
29 tst r0, r0
31 bx r0
47 mrceq p15, 0, r0, c1, c0, 1 /* actlr */
48 orreq r0, r0, #(1<<7)
49 mcreq p15, 0, r0, c1, c0, 1
52 mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
53 and r0, r0, #0xf00
54 lsr r0, r0, #8
55 tst r0, #1 /* only need for cluster 0 */
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm946es/
H A Dstart.S40 mrs r0,cpsr
41 bic r0,r0,#0x1f
42 orr r0,r0,#0xd3
43 msr cpsr,r0
79 mov r0, #0
80 mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */
81 mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */
86 mrc p15, 0, r0, c1, c0, 0
87 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
88 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/sa1100/
H A Dstart.S34 mrs r0,cpsr
35 bic r0,r0,#0x1f
36 orr r0,r0,#0xd3
37 msr cpsr,r0
90 ldr r0, IC_BASE
92 str r1, [r0, #ICMR]
95 ldr r0, PWR_BASE
97 str r1, [r0, #PPCR]
113 mrc p15,0,r0,c1,c0
114 bic r0, r0, #0x00002000 @ clear bit 13 (X)
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/spear/
H A Dspr_lowlevel_init.S23 stmfd sp!,{r0-r12}
29 mov r4,r0
33 ldr r0,DDR_07_V
34 ldr r1,[r0]
37 str r1,[r0]
38 ldr r0,DDR_57_V
39 ldr r1,[r0]
44 str r1,[r0]
45 ldr r0,DDR_07_V
46 ldr r1,[r0]
[all …]
/rk3399_rockchip-uboot/arch/arm/lib/
H A Dcrt0.S74 ldr r0, =(CONFIG_TPL_STACK)
76 ldr r0, =(CONFIG_SPL_STACK)
78 ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
80 bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
81 mov sp, r0
83 mov sp, r0
85 mov r9, r0
99 ldr r0, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */
100 bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
101 mov sp, r0
[all …]

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