Lines Matching refs:r0
24 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
25 orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
26 mcr p15, 0, r0, c1, c0, 0
43 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
44 bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
45 mcr p15, 0, r0, c1, c0, 0
54 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
55 bic r0, r0, #0x37
56 orr r0, r0, #0x20 @ disable TTBR1
57 mcr p15, 0, r0, c2, c0, 2
59 orr r0, r12, #0x8 @ Outer Cacheability for table walks: WBWA
60 mcr p15, 0, r0, c2, c0, 0 @ TTBR0
62 mov r0, #0
63 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
65 mov r0, #-1 @ manager for all domains (No permission check)
66 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
75 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
76 orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
77 mcr p15, 0, r0, c1, c0, 0
103 0: ldr r0, = 0x00408006 @ touch to zero with address range
104 str r0, [r1, #SSCOQM]
105 ldr r0, = BOOT_RAM_BASE
106 str r0, [r1, #SSCOQAD]
107 ldr r0, = BOOT_RAM_SIZE
108 str r0, [r1, #SSCOQSZ]
109 ldr r0, = BOOT_RAM_WAYS
110 str r0, [r1, #SSCOQWN]
111 ldr r0, [r1, #SSCOPPQSEF]
112 cmp r0, #0 @ check if the command is successfully set
115 1: ldr r0, [r1, #SSCOLPQS]
116 cmp r0, #0x4
118 str r0, [r1, #SSCOLPQS] @ clear the complete notification flag
127 ldr r0, = DEVICE
130 0: str r0, [r1], #4 @ specify all the sections as Device
131 adds r0, r0, #0x00100000
134 ldr r0, = NORMAL
135 str r0, [r12] @ mark the first section as Normal
136 add r0, r0, #0x00100000
137 str r0, [r12, #4] @ mark the second section as Normal