| /rk3399_rockchip-uboot/include/ |
| H A D | generic-phy-dp.h | 26 unsigned int link_rate; member
|
| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | analogix_dp.c | 203 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); in analogix_dp_link_start()
212 buf[0] = dp->link_train.link_rate; in analogix_dp_link_start()
486 dp->link_train.link_rate = reg; in analogix_dp_process_equalizer_training()
491 dp->link_train.link_rate, dp->link_train.lane_count); in analogix_dp_process_equalizer_training()
536 static bool analogix_dp_link_config_validate(u8 link_rate, u8 lane_count) in analogix_dp_link_config_validate() argument
538 switch (link_rate) { in analogix_dp_link_config_validate()
595 dp->link_train.link_rate = analogix_dp_select_link_rate_from_table(dp); in analogix_dp_select_rx_bandwidth()
601 dp->link_train.link_rate = min_t(u32, dp->link_train.link_rate, in analogix_dp_select_rx_bandwidth()
603 if (!dp->link_train.link_rate) in analogix_dp_select_rx_bandwidth()
1012 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate), in analogix_dp_get_output_format_by_edid()
[all …]
|
| H A D | drm_dp_helper.c | 137 u8 drm_dp_link_rate_to_bw_code(int link_rate) in drm_dp_link_rate_to_bw_code() argument
140 return link_rate / 27000; in drm_dp_link_rate_to_bw_code()
|
| H A D | analogix_dp_reg.c | 724 phy_cfg.dp.link_rate = in analogix_dp_set_link_bandwidth()
725 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100; in analogix_dp_set_link_bandwidth()
806 phy_cfg.dp.link_rate = in analogix_dp_set_lane_link_training()
807 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100; in analogix_dp_set_lane_link_training()
|
| H A D | analogix_dp.h | 613 u8 link_rate; member
|
| H A D | dw-dp.c | 609 phy_cfg.dp.link_rate = link->rate / 100; in dw_dp_link_train_update_vs_emph()
639 phy_cfg.dp.link_rate = link->rate / 100; in dw_dp_link_configure()
1014 phy_cfg.dp.link_rate = link->rate / 100; in dw_dp_set_phy_default_config()
|
| /rk3399_rockchip-uboot/drivers/video/rockchip/ |
| H A D | rk_edp.c | 328 values[0] = edp->link_train.link_rate; in rk_edp_link_configure()
600 edp->link_train.link_rate = values[1]; in rk_edp_init_training()
604 edp->link_train.link_rate * 27 / 100, in rk_edp_init_training()
605 edp->link_train.link_rate * 27 % 100, in rk_edp_init_training()
608 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) && in rk_edp_init_training()
609 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) { in rk_edp_init_training()
611 edp->link_train.link_rate); in rk_edp_init_training()
635 writel(edp->link_train.link_rate, &edp->regs->link_bw_set); in rk_edp_hw_link_training()
|
| /rk3399_rockchip-uboot/drivers/video/drm/display-serdes/ |
| H A D | core.h | 258 u32 link_rate; member
273 u32 link_rate; member
|
| /rk3399_rockchip-uboot/drivers/phy/ |
| H A D | phy-rockchip-samsung-hdptx.c | 671 switch (dp->link_rate) { in rockchip_hdptx_phy_verify_config()
713 switch (dp->link_rate) { in rockchip_hdptx_phy_set_voltage()
866 static bool is_extra_recommended_link_rate(u32 link_rate) in is_extra_recommended_link_rate() argument
868 switch (link_rate) { in is_extra_recommended_link_rate()
896 switch (dp->link_rate) { in rockchip_hdptx_phy_set_rate()
926 if (is_extra_recommended_link_rate(dp->link_rate)) { in rockchip_hdptx_phy_set_rate()
975 if (is_extra_recommended_link_rate(dp->link_rate)) { in rockchip_hdptx_phy_set_rate()
|
| H A D | phy-rockchip-naneng-edp.c | 177 switch (dp->link_rate) { in rockchip_edp_phy_set_rate()
249 switch (dp->link_rate) { in rockchip_edp_phy_verify_config()
|
| H A D | phy-rockchip-usbdp.c | 1003 switch (dp->link_rate) { in rockchip_dpphy_verify_config()
1057 switch (dp->link_rate) { in dp_phy_set_rate()
1122 switch (dp->link_rate) { in dp_phy_set_voltages()
|
| /rk3399_rockchip-uboot/drivers/video/tegra124/ |
| H A D | dp.c | 488 const u32 link_rate = 27 * link_cfg->link_bw * 1000 * 1000; in tegra_dc_dp_calc_config() local
510 if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ || in tegra_dc_dp_calc_config()
515 (u64)link_rate * 8 * link_cfg->lane_count) in tegra_dc_dp_calc_config()
518 num_linkclk_line = (u32)(lldiv(link_rate * timing->hactive.typ, in tegra_dc_dp_calc_config()
523 do_div(ratio_f, link_rate * link_cfg->lane_count); in tegra_dc_dp_calc_config()
624 link_rate, timing->pixelclock.typ) - in tegra_dc_dp_calc_config()
640 * link_rate, timing->pixelclock.typ) - (36 / in tegra_dc_dp_calc_config()
|
| /rk3399_rockchip-uboot/drivers/video/drm/display-serdes/maxim/ |
| H A D | maxim-max96772.c | 330 serdes_reg_write(serdes, 0xe790, serdes->serdes_panel->link_rate); in max96772_panel_prepare()
340 switch (serdes->serdes_panel->link_rate) { in max96772_panel_prepare()
397 drm_dp_bw_code_to_link_rate(serdes->serdes_panel->link_rate)); in max96772_panel_prepare()
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | edp_rk3288.h | 632 u8 link_rate; member
|
| /rk3399_rockchip-uboot/include/drm/ |
| H A D | drm_dp_helper.h | 1022 u8 drm_dp_link_rate_to_bw_code(int link_rate);
|