video/drm: analogix_dp: Add support to enable clk and pd for mos

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ib010430e1d6eebcfb7d42b365273b438f6d5df9a

video/drm: analogix_dp: support for switching the eDP/DP mode

Since the Analogix IP can support both eDP v1.3 and DP v1.2, it is
sensible to first check whether the last bridge is connected to a
pan

video/drm: analogix_dp: support for switching the eDP/DP mode

Since the Analogix IP can support both eDP v1.3 and DP v1.2, it is
sensible to first check whether the last bridge is connected to a
panel in order to determine and pass on the eDP/DP submodes to the
PHY, which can help separate the eDP/DP configurations in the PHY
driver.

Change-Id: I802b3e2052a9869412d7b9e70e96fe8da0203b9f
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: analogix_dp: add support for ASSR mode

According to the eDP v1.3 chapter 3.6 Table 3-15, Alternative
Scramble Seed Reset(ASSR) is a recommended way for eDP Sink devices
to support Display

video/drm: analogix_dp: add support for ASSR mode

According to the eDP v1.3 chapter 3.6 Table 3-15, Alternative
Scramble Seed Reset(ASSR) is a recommended way for eDP Sink devices
to support Display Authentication and Content Protection as Method
3a, while Method 1 HDCP is normally not expected in an eDP Sink
device.

In addition, the ASSR support capability should be the bit 0 of
DPCD register 0000Dh according to the eDP v1.4 'Revision History'
table 2:

......
Table 3-4: Corrected reference to DPCD Address 0000Dh, bit 0 (was bit 4)
......

Change-Id: I311a8ed0baae37047e84bdc697842c5bb3fcd6fb
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: analogix_dp: add support for color format yuv444/yuv422

The detailed changes as follows:
1.Add flag max_bpc and format_yuv to check whether the platform
support 10 bit per component and

video/drm: analogix_dp: add support for color format yuv444/yuv422

The detailed changes as follows:
1.Add flag max_bpc and format_yuv to check whether the platform
support 10 bit per component and YUV444/YUV422.
2.Add exact bpp related to output format in bandwidth calculation,
which is fixed to 24 before the patch.
3.Add .get_timing() of rockchip_connector_funcs support to meet the
needs of epd2dp application cases.

Related kernel commit:
a7620fa846c2 ("drm/rockchip: analogix_dp: add support for color format yuv444/yuv422")

Change-Id: I6c8e8cfbbc653a6e4ab86d39fb974657e917d037
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: analogix_dp: read/write DPCD through drm_dp_aux

Sync the functions of DPCD read/write with Kernel:

analogix_dp_write_byte_to_dpcd() -> drm_dp_dpcd_writeb()
analogix_dp_read_byte_from_dpc

video/drm: analogix_dp: read/write DPCD through drm_dp_aux

Sync the functions of DPCD read/write with Kernel:

analogix_dp_write_byte_to_dpcd() -> drm_dp_dpcd_writeb()
analogix_dp_read_byte_from_dpcd() -> drm_dp_dpcd_readb()
analogix_dp_write_bytes_to_dpcd() -> drm_dp_dpcd_write()
analogix_dp_read_bytes_from_dpcd() -> drm_dp_dpcd_read()

In addition, the older functions may not have the return value check.
So the necessary return value check have been added in the patch, which
is also synchronized with Kernel.

With the patch, the analogix_dp driver will be more maintainable and
readable.

Change-Id: Ic2b7d6d9ab32ecec0c5bb6de09082c536cae1a41
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: analogix_dp: register drm_dp_aux and support the transfer function of aux

Change-Id: Iccb0a170d73fe6e7960ca759015b38bd5c9d70da
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

video/drm: analogix_dp: add support for rate R216/R243/R324/R432

R216/R243/R324/R432 are the new recommended link rates in
eDP v1.4, which may be read from DPCD SUPPORTED_LINK_RATES
(0x00010h throug

video/drm: analogix_dp: add support for rate R216/R243/R324/R432

R216/R243/R324/R432 are the new recommended link rates in
eDP v1.4, which may be read from DPCD SUPPORTED_LINK_RATES
(0x00010h through 0x0001fh). And set the link rate by DPCD
LINK_BW_SET(0x00100h).

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I68ed7020c87e9e4453128890e3ca42b875455b80

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video/drm: analogix_dp: add support to parse link rate for eDP v1.4

As Table 4-23 in eDP v1.4 spec, the link rate can be
read from SUPPORTED_LINK_RATES(0x00010h through 0x0001fh),
which is required

video/drm: analogix_dp: add support to parse link rate for eDP v1.4

As Table 4-23 in eDP v1.4 spec, the link rate can be
read from SUPPORTED_LINK_RATES(0x00010h through 0x0001fh),
which is required for sink devices.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: If747462b9c4b37ee643e9ca08e4daf397cbdce9d

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video/drm: analogix_dp: add support for rk3576

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ieceb5038f1e94a2a4ea40921a1266d4d4d28847e

video/drm: analogix_dp: Fix stream valid control

Fixes: e9cac7f1fea9 ("video/drm: analogix_dp: Use video format information from register")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id

video/drm: analogix_dp: Fix stream valid control

Fixes: e9cac7f1fea9 ("video/drm: analogix_dp: Use video format information from register")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I94c32572bc8b58cc5902a1ada23f45f300d06ca5

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video/drm: support for multi connector

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Id87d4c81e60a9f69f3fbfc05ffd67a3d42cd21a4

video/drm: analogix_dp: Support DT specified physical-logical lane mappings

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ic61ba6f12b24f4179441430794c7641c9cd6753e

video/drm: analogix_dp: support video BIST generation

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I4e17a0215f6114e3cb02867e6800ab060f384ca7

video/drm: analogix_dp: Set link power state

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I69e08c0d010dfc94e375c9c107abe9e14d7f4b70

video/drm: analogix_dp: Use link train delay helper

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Iba67c1d1dfc7ad62cf95cd95b212fe1abdfa69c0

video/drm: analogix_dp: Add support for rk3588

Change-Id: I4cbfc252fefa6819e74d74e59ffd4ab7494f4001
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>

video/drm: analogix_dp: Fix display corruption in low temperature environment

Change-Id: I2b2bbbd93d0f7b315afefa14720acab5ccd31c6d
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>

drm/rockchip: drv: init connector id and get disp info from baseparameter2

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I4a602b826ca2a61692fff5e9c664f4e45eee0351

video/drm: analogix_dp: Add support for rk3568

This patch adds support for Analogix eDP TX IP used on RK3568 SoC.

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ia48f1f99f336d4d98d5fba

video/drm: analogix_dp: Add support for rk3568

This patch adds support for Analogix eDP TX IP used on RK3568 SoC.

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ia48f1f99f336d4d98d5fba4e5fd15a35bdbaf373

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video/drm: Add dp helper

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I559f7288038c9b1128f64e56ea7f156a1f643f33

video/drm: analogix_dp: Simplify analogix_dp_{set/get}_lane_link_training helpers

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I5e0a90c8a1fd132567635a7751c1ca4ade38e692

video/drm: analogix_dp: Implement detect callback

Change-Id: I1e6746768092747920afcb3af07e36c1ecae9856
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>

video/drm: analogix_dp: add edp reset control support

This patch adds eDP software reset operation to make sure
register access successfully on RK3288 and it fixes possible
register default value ab

video/drm: analogix_dp: add edp reset control support

This patch adds eDP software reset operation to make sure
register access successfully on RK3288 and it fixes possible
register default value abnormal issue during boot up.

1) normal case:
Rockchip UBOOT DRM driver version: v1.0.1
0x120: 0x00000007
0x390: 0x00000003
Using display timing dts
Detailed mode clock 200000 kHz, flags[a]
H: 1536 1548 1564 1612
V: 2048 2056 2060 2068
bus_format: 100e
Link Training success!
final link rate = 0x06, lane count = 0x04

2) abnormal case:
Rockchip UBOOT DRM driver version: v1.0.1
0x120: 0x00000066
0x390: 0x00000202
Using display timing dts
Detailed mode clock 200000 kHz, flags[a]
H: 1536 1548 1564 1612
V: 2048 2056 2060 2068
bus_format: 100e
failed to get Rx Max Link Rate
failed to init training
unable to do link train

Change-Id: Idacbb0c72a40442da3a87e60bfe1d9965f3ca79c
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>

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video/drm: Rename rockchip_analogix_dp to analogix_dp

Change-Id: I5603a709abde6a852fcca0b3a5b833727d5f3cad
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>