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Searched refs:iobase (Results 1 – 25 of 85) sorted by relevance

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/rk3399_rockchip-uboot/drivers/net/
H A Dravb.c123 void __iomem *iobase; member
153 if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0)) in ravb_send()
154 setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0); in ravb_send()
220 writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC); in ravb_reset()
223 return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR, in ravb_reset()
241 writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT); in ravb_base_desc_init()
337 eth->iobase + RAVB_REG_MAHR); in ravb_write_hwaddr()
339 writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR); in ravb_write_hwaddr()
348 writel(0, eth->iobase + RAVB_REG_ECSIPR); in ravb_mac_init()
351 writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR); in ravb_mac_init()
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H A Dsmc91111.h72 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1))))
73 #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
75 unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \
81 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
82 #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r))))
84 unsigned int __p = (unsigned int)((a)->iobase + (p)); \
92 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d)
93 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d)
95 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
96 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d)
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H A Dftmac100.c28 phys_addr_t iobase; member
36 struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase; in ftmac100_reset()
52 struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase; in ftmac100_set_mac()
67 struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase; in _ftmac100_halt()
77 struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase; in _ftmac100_init()
184 struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase; in _ftmac100_send()
294 dev->iobase = CONFIG_FTMAC100_BASE; in ftmac100_initialize()
300 priv->iobase = dev->iobase; in ftmac100_initialize()
395 pdata->iobase = devfdt_get_addr(dev); in ftmac100_ofdata_to_platdata()
396 priv->iobase = pdata->iobase; in ftmac100_ofdata_to_platdata()
H A Dpcnet.c98 outw(index, dev->iobase + PCNET_RAP); in pcnet_read_csr()
99 return inw(dev->iobase + PCNET_RDP); in pcnet_read_csr()
104 outw(index, dev->iobase + PCNET_RAP); in pcnet_write_csr()
105 outw(val, dev->iobase + PCNET_RDP); in pcnet_write_csr()
110 outw(index, dev->iobase + PCNET_RAP); in pcnet_read_bcr()
111 return inw(dev->iobase + PCNET_BDP); in pcnet_read_bcr()
116 outw(index, dev->iobase + PCNET_RAP); in pcnet_write_bcr()
117 outw(val, dev->iobase + PCNET_BDP); in pcnet_write_bcr()
122 inw(dev->iobase + PCNET_RESET); in pcnet_reset()
127 outw(88, dev->iobase + PCNET_RAP); in pcnet_check()
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H A Duli526x.c210 u32 iobase; in uli526x_initialize() local
219 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); in uli526x_initialize()
220 iobase &= ~0xf; in uli526x_initialize()
234 dev->iobase = iobase; in uli526x_initialize()
242 db->ioaddr = dev->iobase; in uli526x_initialize()
247 printf("uli526x: uli526x @0x%x\n", iobase); in uli526x_initialize()
351 update_cr6(db->cr6_data, dev->iobase); in uli526x_disable()
352 outl(0, dev->iobase + DCR7); /* Disable Interrupt */ in uli526x_disable()
353 outl(inl(dev->iobase + DCR5), dev->iobase + DCR5); in uli526x_disable()
459 outl(0, dev->iobase + DCR7); in uli526x_start_xmit()
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H A Drtl8169.c327 ulong iobase; member
588 return rtl_recv_common(dev, priv->iobase, packetp); in rtl8169_eth_recv()
594 dev->iobase, NULL); in rtl_recv()
684 return rtl_send_common(dev, priv->iobase, packet, length); in rtl8169_eth_send()
691 dev->iobase, packet, length); in rtl_send()
892 rtl8169_common_start(dev, plat->enetaddr, priv->iobase); in rtl8169_eth_start()
903 dev->enetaddr, dev->iobase); in rtl_reset()
937 rtl_halt_common(priv->iobase); in rtl8169_eth_stop()
945 rtl_halt_common(dev->iobase); in rtl_halt()
1106 u32 iobase; in rtl8169_initialize() local
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H A Dat91_emac.c159 return (at91_emac_t *) netdev->iobase; in get_emacbase_by_name()
191 emac = (at91_emac_t *) netdev->iobase; in at91emac_phy_reset()
226 emac = (at91_emac_t *) netdev->iobase; in at91emac_phy_init()
325 emac = (at91_emac_t *) netdev->iobase; in at91emac_init()
387 emac = (at91_emac_t *) netdev->iobase; in at91emac_halt()
397 emac = (at91_emac_t *) netdev->iobase; in at91emac_send()
417 emac = (at91_emac_t *) netdev->iobase; in at91emac_recv()
455 emac = (at91_emac_t *) netdev->iobase; in at91emac_write_hwaddr()
472 int at91emac_register(bd_t *bis, unsigned long iobase) in at91emac_register() argument
478 if (iobase == 0) in at91emac_register()
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H A Drtl8139.c208 u32 iobase; in rtl8139_initialize() local
216 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); in rtl8139_initialize()
217 iobase &= ~0xf; in rtl8139_initialize()
219 debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase); in rtl8139_initialize()
231 dev->iobase = (int)bus_to_phys(iobase); in rtl8139_initialize()
258 ioaddr = dev->iobase; in rtl8139_probe()
417 ioaddr = dev->iobase; in rtl_transmit()
473 ioaddr = dev->iobase; in rtl_poll()
529 ioaddr = dev->iobase; in rtl_disable()
H A Dax88180.h358 return le16_to_cpu(readw(addr + (void *)dev->iobase)); in INW()
367 writew(cpu_to_le16(command), addr + (void *)dev->iobase); in OUTW()
372 return le16_to_cpu(readw(RXBUFFER_START + (void *)dev->iobase)); in READ_RXBUF()
377 writew(cpu_to_le16(data), TXBUFFER_START + (void *)dev->iobase); in WRITE_TXBUF()
382 writel(cpu_to_le32(command), addr + (void *)dev->iobase); in OUTW()
387 return le32_to_cpu(readl(RXBUFFER_START + (void *)dev->iobase)); in READ_RXBUF()
392 writel(cpu_to_le32(data), TXBUFFER_START + (void *)dev->iobase); in WRITE_TXBUF()
H A Dks8851_mll.c111 writew(offset | (BE0 << shift_bit), dev->iobase + 2); in ks_rdreg8()
113 return (u8)(readw(dev->iobase) >> shift_data); in ks_rdreg8()
118 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2); in ks_rdreg16()
120 return readw(dev->iobase); in ks_rdreg16()
128 writew(offset | (BE0 << shift_bit), dev->iobase + 2); in ks_wrreg8()
129 writew(value_write, dev->iobase); in ks_wrreg8()
134 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2); in ks_wrreg16()
135 writew(val, dev->iobase); in ks_wrreg16()
150 *wptr++ = readw(dev->iobase); in ks_inblk()
164 writew(*wptr++, dev->iobase); in ks_outblk()
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H A Dxilinx_axi_emac.c88 struct axi_regs *iobase; member
170 struct axi_regs *regs = priv->iobase; in phyread()
196 struct axi_regs *regs = priv->iobase; in phywrite()
225 struct axi_regs *regs = priv->iobase; in axiemac_phy_init()
270 struct axi_regs *regs = priv->iobase; in setup_phy()
352 struct axi_regs *regs = priv->iobase; in axi_ethernet_init()
403 struct axi_regs *regs = priv->iobase; in axiemac_write_hwaddr()
442 struct axi_regs *regs = priv->iobase; in axiemac_start()
695 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); in axi_emac_ofdata_to_platdata()
696 priv->iobase = (struct axi_regs *)pdata->iobase; in axi_emac_ofdata_to_platdata()
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H A Dftgmac100.c48 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_mdiobus_read()
83 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_mdiobus_write()
254 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_update_link_speed()
321 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_reset()
337 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_set_mac()
359 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_halt()
368 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_init()
511 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_send()
566 dev->iobase = CONFIG_FTGMAC100_BASE; in ftgmac100_initialize()
H A Dnatsemi.c255 return le16_to_cpu(*(vu_short *) (addr + dev->iobase)); in INW()
261 return le32_to_cpu(*(vu_long *) (addr + dev->iobase)); in INL()
267 *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command); in OUTW()
273 *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command); in OUTL()
295 u32 iobase, status, chip_config; in natsemi_initialize() local
306 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); in natsemi_initialize()
307 iobase &= ~0x3; /* bit 1: unused and bit 0: I/O Space Indicator */ in natsemi_initialize()
330 dev->iobase = bus_to_phys(iobase); in natsemi_initialize()
332 printf("natsemi: NatSemi ns8381[56] @ %#x\n", dev->iobase); in natsemi_initialize()
446 dev->iobase + ee_addr, write_cmd, value);
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/rk3399_rockchip-uboot/drivers/ata/
H A Dsata_sil3114.c38 static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */ variable
371 u32 port = iobase[5]; in wait_for_irq()
655 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]); in init_sata()
656 pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]); in init_sata()
657 pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]); in init_sata()
658 pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]); in init_sata()
659 pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]); in init_sata()
660 pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]); in init_sata()
662 if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) || in init_sata()
663 (iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) || in init_sata()
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/rk3399_rockchip-uboot/drivers/misc/
H A Dsmsc_sio1007.c30 void sio1007_enable_serial(int port, int num, int iobase, int irq) in sio1007_enable_serial() argument
41 sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2); in sio1007_enable_serial()
45 sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2); in sio1007_enable_serial()
53 void sio1007_enable_runtime(int port, int iobase) in sio1007_enable_runtime() argument
59 sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4); in sio1007_enable_runtime()
60 sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12); in sio1007_enable_runtime()
H A Dwinbond_w83627.c32 void winbond_enable_serial(uint dev, uint iobase, uint irq) in winbond_enable_serial() argument
37 pnp_set_iobase(dev, PNP_IDX_IO0, iobase); in winbond_enable_serial()
H A Dsmsc_lpc47m.c25 void lpc47m_enable_serial(uint dev, uint iobase, uint irq) in lpc47m_enable_serial() argument
30 pnp_set_iobase(dev, PNP_IDX_IO0, iobase); in lpc47m_enable_serial()
/rk3399_rockchip-uboot/arch/x86/lib/
H A Dpinctrl_ich6.c62 static int ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node) in ich6_pinctrl_cfg_pin() argument
106 if (iobase != -1) { in ich6_pinctrl_cfg_pin()
121 iobase_addr = iobase + pad_offset; in ich6_pinctrl_cfg_pin()
159 u32 iobase = -1; in ich6_pinctrl_probe() local
184 ret = pch_get_io_base(pch, &iobase); in ich6_pinctrl_probe()
186 debug("%s: invalid IOBASE address (%08x)\n", __func__, iobase); in ich6_pinctrl_probe()
194 ret = ich6_pinctrl_cfg_pin(gpiobase, iobase, pin_node); in ich6_pinctrl_probe()
/rk3399_rockchip-uboot/board/micronas/vct/
H A Debi_smc911x.c40 addr += dev->iobase; in smc911x_reg_read()
52 addr += dev->iobase; in smc911x_reg_write()
63 addr += dev->iobase; in pkt_data_push()
78 addr += dev->iobase; in pkt_data_pull()
/rk3399_rockchip-uboot/arch/x86/include/asm/
H A Dpnp_def.h68 static inline void pnp_set_iobase(uint16_t dev, uint8_t index, uint16_t iobase) in pnp_set_iobase() argument
70 pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); in pnp_set_iobase()
71 pnp_write_config(dev, index + 1, iobase & 0xff); in pnp_set_iobase()
/rk3399_rockchip-uboot/board/renesas/rsk7264/
H A Drsk7264.c42 volatile u16 *addr_16 = (u16 *)(dev->iobase + addr); in pkt_data_pull()
49 addr += dev->iobase; in pkt_data_push()
/rk3399_rockchip-uboot/board/renesas/rsk7203/
H A Drsk7203.c41 volatile u16 *addr_16 = (u16 *)(dev->iobase + addr); in pkt_data_pull()
48 addr += dev->iobase; in pkt_data_push()
/rk3399_rockchip-uboot/board/renesas/rsk7269/
H A Drsk7269.c43 volatile u16 *addr_16 = (u16 *)(dev->iobase + addr); in pkt_data_pull()
50 addr += dev->iobase; in pkt_data_push()
/rk3399_rockchip-uboot/drivers/clk/
H A Dclk_pic32.c88 void __iomem *iobase; member
97 v = readl(priv->iobase + SPLLCON); in pic32_get_pll_rate()
123 v = readl(priv->iobase + OSCCON); in pic32_get_sysclk()
159 reg = priv->iobase + PB1DIV + (periph - PB1CLK) * 0x10; in pic32_get_pbclk()
194 reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20; in pic32_set_refclk()
238 reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20; in pic32_get_refclk()
401 priv->iobase = ioremap(addr, size); in pic32_clk_probe()
402 if (!priv->iobase) in pic32_clk_probe()
/rk3399_rockchip-uboot/include/
H A Dsmsc_sio1007.h73 void sio1007_enable_serial(int port, int num, int iobase, int irq);
82 void sio1007_enable_runtime(int port, int iobase);

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