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Searched refs:bnds (Results 1 – 17 of 17) sorted by relevance

/rk3399_rockchip-uboot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c79 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
80 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
81 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
82 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
111 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
112 .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
113 .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
114 .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
143 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
144 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
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/rk3399_rockchip-uboot/drivers/ddr/fsl/
H A Dmpc85xx_ddr_gen3.c75 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; in fsl_ddr_set_memctl_regs()
76 cs_ea = regs->cs[i].bnds & 0xfff; in fsl_ddr_set_memctl_regs()
79 csn_bnds_backup = regs->cs[i].bnds; in fsl_ddr_set_memctl_regs()
80 csn_bnds_t = (unsigned int *) &regs->cs[i].bnds; in fsl_ddr_set_memctl_regs()
82 *csn_bnds_t = regs->cs[i].bnds + 0x01000000; in fsl_ddr_set_memctl_regs()
84 *csn_bnds_t = regs->cs[i].bnds + 0x01000100; in fsl_ddr_set_memctl_regs()
87 csn, csn_bnds_backup, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
94 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
99 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
104 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
[all …]
H A Dmpc85xx_ddr_gen1.c29 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
33 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
37 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
41 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
H A Dmpc86xx_ddr.c35 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
39 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
43 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
47 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
H A Dmpc85xx_ddr_gen2.c50 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
54 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
58 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
62 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
H A Darm_ddr_gen3.c71 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
76 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
81 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
86 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
H A Dfsl_ddr_gen4.c105 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
110 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
115 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
120 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
H A Dinteractive.c600 CFG_REGS_CS(0, bnds), in print_fsl_memctl_config_regs()
604 CFG_REGS_CS(1, bnds), in print_fsl_memctl_config_regs()
609 CFG_REGS_CS(2, bnds), in print_fsl_memctl_config_regs()
614 CFG_REGS_CS(3, bnds), in print_fsl_memctl_config_regs()
690 CFG_REGS_CS(0, bnds), in fsl_ddr_regs_edit()
694 CFG_REGS_CS(1, bnds), in fsl_ddr_regs_edit()
699 CFG_REGS_CS(2, bnds), in fsl_ddr_regs_edit()
704 CFG_REGS_CS(3, bnds), in fsl_ddr_regs_edit()
H A Dmain.c606 if (reg->cs[j].bnds == 0xffffffff) in fsl_ddr_compute()
608 end = reg->cs[j].bnds & 0xffff; in fsl_ddr_compute()
H A Dctrl_regs.c2477 ddr->cs[i].bnds = (0 in compute_fsl_memctl_config_regs()
2483 ddr->cs[i].bnds = 0xffffffff; in compute_fsl_memctl_config_regs()
2486 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); in compute_fsl_memctl_config_regs()
/rk3399_rockchip-uboot/board/freescale/p1_twr/
H A Dddr.c23 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, in fixed_sdram()
27 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, in fixed_sdram()
/rk3399_rockchip-uboot/board/freescale/p1010rdb/
H A Dddr.c22 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
49 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
138 ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff; in fixed_sdram()
/rk3399_rockchip-uboot/board/Arcturus/ucp1020/
H A Dddr.c83 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, in fixed_sdram()
87 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, in fixed_sdram()
/rk3399_rockchip-uboot/board/freescale/bsc9132qds/
H A Dddr.c21 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
48 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
/rk3399_rockchip-uboot/board/freescale/p1_p2_rdb_pc/
H A Dddr.c215 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, in fixed_sdram()
219 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, in fixed_sdram()
/rk3399_rockchip-uboot/board/freescale/bsc9131rdb/
H A Dddr.c22 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
/rk3399_rockchip-uboot/include/
H A Dfsl_ddr_sdram.h244 unsigned int bnds; member