| /rk3399_ARM-atf/plat/xilinx/common/include/ |
| H A D | pm_api_sys.h | 67 #define PM_PACK_PAYLOAD3(pl, mid, flag, arg0, arg1, arg2) { \ argument
68 pl[2] = (uint32_t)(arg2); \
72 #define PM_PACK_PAYLOAD4(pl, mid, flag, arg0, arg1, arg2, arg3) { \ argument
74 PM_PACK_PAYLOAD3(pl, (mid), (flag), (arg0), (arg1), (arg2)); \
77 #define PM_PACK_PAYLOAD5(pl, mid, flag, arg0, arg1, arg2, arg3, arg4) { \ argument
79 PM_PACK_PAYLOAD4(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3)); \
82 #define PM_PACK_PAYLOAD6(pl, mid, flag, arg0, arg1, arg2, arg3, arg4, arg5) { \ argument
84 PM_PACK_PAYLOAD5(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3), (arg4)); \
87 #define PM_PACK_PAYLOAD7(pl, mid, flag, arg0, arg1, arg2, arg3, arg4, arg5, arg6) { \ argument
89 PM_PACK_PAYLOAD6(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3), (arg4), (arg5)); \
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| /rk3399_ARM-atf/bl32/tsp/ |
| H A D | tsp_private.h | 53 uint64_t arg2,
61 uint64_t arg2,
69 uint64_t arg2,
78 uint64_t arg2,
108 uint64_t arg2,
117 uint64_t arg2,
126 uint64_t arg2,
135 uint64_t arg2,
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| H A D | tsp_common.c | 36 uint64_t arg2, in set_smc_args() argument
54 write_sp_arg(pcpu_smc_args, SMC_ARG2, arg2); in set_smc_args()
67 void tsp_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, in tsp_setup() argument
74 tsp_early_platform_setup(arg0, arg1, arg2, arg3); in tsp_setup()
86 uint64_t arg2, in tsp_system_off_main() argument
114 uint64_t arg2, in tsp_system_reset_main() argument
144 uint64_t arg2, in tsp_abort_smc_handler() argument
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| H A D | tsp_ffa_main.c | 85 uint64_t arg2, in ffa_test_relay() argument
282 uint64_t arg2, in tsp_cpu_off_main() argument
320 uint64_t arg2, in tsp_cpu_suspend_main() argument
357 uint64_t arg2, in tsp_cpu_resume_main() argument
390 uint64_t arg2, in handle_framework_message() argument
403 if ((arg2 & FFA_FWK_MSG_MASK) == FFA_FWK_MSG_PSCI) { in handle_framework_message()
406 return tsp_cpu_off_main(arg0, arg1, arg2, arg3, in handle_framework_message()
409 return tsp_cpu_suspend_main(arg0, arg1, arg2, arg3, in handle_framework_message()
412 } else if ((arg2 & FFA_FWK_MSG_MASK) == FFA_PM_MSG_WB_REQ) { in handle_framework_message()
415 return tsp_cpu_resume_main(arg0, arg1, arg2, arg3, in handle_framework_message()
[all …]
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| /rk3399_ARM-atf/lib/debugfs/ |
| H A D | debugfs_smc.c | 64 u_register_t arg2, in debugfs_smc_handler() argument
87 arg2 &= 0xffffffff; in debugfs_smc_handler()
105 ret = mmap_add_dynamic_region(arg2, in debugfs_smc_handler()
133 ret = open(parms.open.fname, arg2); in debugfs_smc_handler()
141 ret = close(arg2); in debugfs_smc_handler()
149 ret = read(arg2, DEBUGFS_SHARED_BUF_VIRT, arg3); in debugfs_smc_handler()
157 ret = seek(arg2, arg3, arg4); in debugfs_smc_handler()
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| /rk3399_ARM-atf/plat/st/stm32mp2/ |
| H A D | bl31_plat_setup.c | 22 u_register_t arg2, u_register_t arg3) in bl31_early_platform_setup2() argument
99 if (arg2 != 0U) { in bl31_early_platform_setup2()
102 bl33_image_ep_info.args.arg2 = arg2; in bl31_early_platform_setup2()
109 if (arg2 != 0U) { in bl31_early_platform_setup2()
110 bl32_image_ep_info.args.arg3 = arg2; in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/ |
| H A D | mt_spm_dispatcher.c | 48 u_register_t arg1, u_register_t arg2, in mt_spm_dispatcher() argument
60 if (!(arg2 & MT_SPM_STATUS_SUSPEND_SLEEP)) in mt_spm_dispatcher()
71 mt_spm_pcm_wdt(1, arg2); in mt_spm_dispatcher()
73 mt_spm_pcm_wdt(0, arg2); in mt_spm_dispatcher()
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| /rk3399_ARM-atf/plat/mediatek/drivers/dfd/ |
| H A D | dfd.c | 14 u_register_t arg2, u_register_t arg3, in dfd_smc_dispatcher() argument
22 dfd_setup(arg1, arg2, arg3); in dfd_smc_dispatcher()
33 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
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| /rk3399_ARM-atf/plat/arm/board/fvp/sp_min/ |
| H A D | fvp_sp_min_setup.c | 20 u_register_t arg2, u_register_t arg3) in plat_arm_sp_min_early_platform_setup() argument
41 assert(arg2 > (uintptr_t)tl && arg2 < (uintptr_t)tl + tl->size); in plat_arm_sp_min_early_platform_setup()
42 hw_config = (uintptr_t)arg2; in plat_arm_sp_min_early_platform_setup()
56 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
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| /rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/ |
| H A D | mt_cpu_pm_smc.c | 34 u_register_t arg2, in cpupm_dispatcher() argument
42 res = mtk_cpc_handler(act, arg1, arg2); in cpupm_dispatcher()
54 u_register_t arg2, in cpupm_lp_dispatcher() argument
64 res = mtk_cpc_handler(act, arg1, arg2); in cpupm_lp_dispatcher()
159 u_register_t arg2, in secure_cpupm_dispatcher() argument
167 res = mtk_cpc_trace_dump(act, arg1, arg2); in secure_cpupm_dispatcher()
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| /rk3399_ARM-atf/drivers/arm/css/scmi/ |
| H A D | scmi_private.h | 100 #define SCMI_PAYLOAD_ARG2(payld_arr, arg1, arg2) do { \ argument
102 mmio_write_32((uintptr_t)&payld_arr[1], arg2); \
105 #define SCMI_PAYLOAD_ARG3(payld_arr, arg1, arg2, arg3) do { \ argument
106 SCMI_PAYLOAD_ARG2(payld_arr, arg1, arg2); \
110 #define SCMI_PAYLOAD_ARG4(payld_arr, arg1, arg2, arg3, arg4) do { \ argument
111 SCMI_PAYLOAD_ARG3(payld_arr, arg1, arg2, arg3); \
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| /rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/ |
| H A D | zynqmp_pm_api_sys.h | 50 #define PM_PACK_PAYLOAD3(pl, flag, arg0, arg1, arg2) { \ argument
51 pl[2] = (uint32_t)(arg2); \
55 #define PM_PACK_PAYLOAD4(pl, flag, arg0, arg1, arg2, arg3) { \ argument
57 PM_PACK_PAYLOAD3(pl, (flag), (arg0), (arg1), (arg2)); \
60 #define PM_PACK_PAYLOAD5(pl, flag, arg0, arg1, arg2, arg3, arg4) { \ argument
62 PM_PACK_PAYLOAD4(pl, (flag), (arg0), (arg1), (arg2), (arg3)); \
65 #define PM_PACK_PAYLOAD6(pl, flag, arg0, arg1, arg2, arg3, arg4, arg5) { \ argument
67 PM_PACK_PAYLOAD5(pl, (flag), (arg0), (arg1), (arg2), (arg3), (arg4)); \
145 uint32_t arg2,
160 void pm_query_data(enum pm_query_ids qid, uint32_t arg1, uint32_t arg2,
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| /rk3399_ARM-atf/plat/arm/board/fvp_ve/sp_min/ |
| H A D | fvp_ve_sp_min_setup.c | 12 u_register_t arg2, u_register_t arg3) in plat_arm_sp_min_early_platform_setup() argument
14 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
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| /rk3399_ARM-atf/plat/arm/board/corstone700/sp_min/ |
| H A D | corstone700_sp_min_setup.c | 10 u_register_t arg2, u_register_t arg3) in plat_arm_sp_min_early_platform_setup() argument
12 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
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| /rk3399_ARM-atf/plat/arm/board/fvp/tsp/ |
| H A D | fvp_tsp_setup.c | 12 u_register_t arg2, u_register_t arg3) in tsp_early_platform_setup() argument
14 arm_tsp_early_platform_setup(arg0, arg1, arg2, arg3); in tsp_early_platform_setup()
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| /rk3399_ARM-atf/plat/arm/board/a5ds/sp_min/ |
| H A D | a5ds_sp_min_setup.c | 12 u_register_t arg2, u_register_t arg3) in plat_arm_sp_min_early_platform_setup() argument
14 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
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| /rk3399_ARM-atf/include/services/ |
| H A D | el3_spmd_logical_sp.h | 30 uint64_t arg2; member
108 return (uint16_t)(args->arg2 & 0xFFFFU); in ffa_partition_info_regs_get_last_idx()
114 return (uint16_t)((args->arg2 >> 16) & 0xFFFFU); in ffa_partition_info_regs_get_curr_idx()
119 return (uint16_t)((args->arg2 >> 32) & 0xFFFFU); in ffa_partition_info_regs_get_tag()
125 return (uint16_t)(args->arg2 >> 48); in ffa_partition_info_regs_get_desc_size()
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| /rk3399_ARM-atf/plat/arm/common/sp_min/ |
| H A D | arm_sp_min_setup.c | 87 u_register_t arg2, u_register_t arg3) in arm_sp_min_early_platform_setup() argument
126 bl33_image_ep_info.args.arg2 = (u_register_t)ARM_PRELOADED_DTB_BASE; in arm_sp_min_early_platform_setup()
165 u_register_t arg2, u_register_t arg3) in plat_arm_sp_min_early_platform_setup() argument
167 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
189 u_register_t arg2, u_register_t arg3) in sp_min_early_platform_setup2() argument
191 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in sp_min_early_platform_setup2()
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| /rk3399_ARM-atf/plat/arm/board/a5ds/ |
| H A D | a5ds_bl2_setup.c | 10 u_register_t arg2, u_register_t arg3) in bl2_early_platform_setup2() argument
12 arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3); in bl2_early_platform_setup2()
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| /rk3399_ARM-atf/bl2/ |
| H A D | bl2_main.c | 42 void __no_pauth bl2_main(u_register_t arg0, u_register_t arg1, u_register_t arg2, in bl2_main() argument
52 bl2_el3_early_platform_setup(arg0, arg1, arg2, arg3); in bl2_main()
58 bl2_early_platform_setup2(arg0, arg1, arg2, arg3); in bl2_main()
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| /rk3399_ARM-atf/plat/st/stm32mp1/sp_min/ |
| H A D | sp_min_setup.c | 114 u_register_t arg2, u_register_t arg3) in sp_min_early_platform_setup2() argument
145 if (arg2 != 0U) { in sp_min_early_platform_setup2()
148 bl33_image_ep_info.args.arg2 = arg2; in sp_min_early_platform_setup2()
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| /rk3399_ARM-atf/plat/arm/board/fvp_ve/ |
| H A D | fvp_ve_bl2_setup.c | 16 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_… in bl2_early_platform_setup2() argument
18 arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3); in bl2_early_platform_setup2()
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| /rk3399_ARM-atf/plat/arm/common/tsp/ |
| H A D | arm_tsp_setup.c | 46 u_register_t arg2, u_register_t arg3) in arm_tsp_early_platform_setup() argument
76 u_register_t arg2, u_register_t arg3) in tsp_early_platform_setup() argument
78 arm_tsp_early_platform_setup(arg0, arg1, arg2, arg3); in tsp_early_platform_setup()
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| /rk3399_ARM-atf/plat/imx/imx7/common/ |
| H A D | imx7_bl2_el3_common.c | 90 bl_mem_params->ep_info.args.arg2 = in bl2_plat_handle_post_image_load()
93 bl_mem_params->ep_info.args.arg2 = 0; in bl2_plat_handle_post_image_load()
150 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, in bl2_el3_early_platform_setup() argument
166 imx7_platform_setup(arg1, arg2, arg3, arg4); in bl2_el3_early_platform_setup()
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/dfd/ |
| H A D | plat_dfd.c | 113 uint64_t arg2, uint64_t arg3) in dfd_smc_dispatcher() argument
119 dfd_setup(arg1, arg2, arg3); in dfd_smc_dispatcher()
130 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
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