| /rk3399_ARM-atf/lib/xlat_tables/aarch32/ |
| H A D | xlat_tables.c | 78 assert((read_sctlr() & SCTLR_M_BIT) == 0U); in enable_mmu_svc_mon()
125 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; in enable_mmu_svc_mon()
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| H A D | nonlpae_tables.c | 516 assert((read_sctlr() & SCTLR_M_BIT) == 0U); in enable_mmu_svc_mon()
551 sctlr |= SCTLR_M_BIT; in enable_mmu_svc_mon()
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| /rk3399_ARM-atf/lib/xlat_tables_v2/aarch64/ |
| H A D | enable_mmu.S | 41 tst x1, #SCTLR_M_BIT
73 mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT
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| H A D | xlat_tables_arch.c | 146 return (read_sctlr_el1() & SCTLR_M_BIT) != 0U; in is_mmu_enabled_ctx()
149 return (read_sctlr_el2() & SCTLR_M_BIT) != 0U; in is_mmu_enabled_ctx()
153 return (read_sctlr_el3() & SCTLR_M_BIT) != 0U; in is_mmu_enabled_ctx()
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| /rk3399_ARM-atf/lib/aarch64/ |
| H A D | misc_helpers.S | 168 tst tmp1, #SCTLR_M_BIT
416 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT)
428 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
438 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT)
450 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
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| /rk3399_ARM-atf/lib/xlat_tables_v2/aarch32/ |
| H A D | enable_mmu.S | 19 tst r1, #SCTLR_M_BIT
57 ldr r2, =(SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT)
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| H A D | xlat_tables_arch.c | 79 return (read_sctlr() & SCTLR_M_BIT) != 0U; in is_mmu_enabled_ctx()
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| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/mce/ |
| H A D | mce.c | 197 if ((sctlr & (uint64_t)SCTLR_M_BIT) == (uint64_t)SCTLR_M_BIT) { in mce_enable_strict_checking()
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| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | wa_cve_2017_5715_mmu.S | 23 bic x1, x1, #SCTLR_M_BIT
27 orr x1, x1, #SCTLR_M_BIT
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| /rk3399_ARM-atf/lib/xlat_tables/aarch64/ |
| H A D | xlat_tables.c | 156 assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0U); \
199 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
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| /rk3399_ARM-atf/plat/nvidia/tegra/lib/debug/ |
| H A D | profiler.c | 100 ((read_sctlr_el3() & SCTLR_M_BIT) != U(0))) { in boot_profiler_add_record()
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| /rk3399_ARM-atf/lib/aarch32/ |
| H A D | misc_helpers.S | 176 mov r1, #(SCTLR_M_BIT | SCTLR_C_BIT)
192 ldr r1, =(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
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| /rk3399_ARM-atf/plat/brcm/common/ |
| H A D | brcm_bl2_setup.c | 100 if (!(read_sctlr_el1() & SCTLR_M_BIT)) { in bcm_bl2_plat_arch_setup()
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/ |
| H A D | plat_pmu_macros.S | 83 bic x10, x9, #(SCTLR_M_BIT)
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| /rk3399_ARM-atf/bl1/ |
| H A D | bl1_main.c | 95 assert((val & SCTLR_M_BIT) != 0); in PMF_REGISTER_SERVICE()
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| /rk3399_ARM-atf/services/std_svc/spm/spm_mm/ |
| H A D | spm_mm_setup.c | 258 SCTLR_M_BIT in spm_sp_setup()
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| /rk3399_ARM-atf/plat/st/common/ |
| H A D | stm32mp_common.c | 119 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT; in stm32mp_lock_available()
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| /rk3399_ARM-atf/docs/security_advisories/ |
| H A D | security-advisory-tfv-3.rst | 74 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
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| /rk3399_ARM-atf/services/std_svc/drtm/ |
| H A D | drtm_main.c | 557 SCTLR_M_BIT in drtm_dl_reset_dlme_el_state()
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| /rk3399_ARM-atf/services/std_svc/spm/el3_spmc/ |
| H A D | spmc_setup.c | 653 SCTLR_M_BIT; in spmc_el0_sp_setup_sctlr_el1()
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| /rk3399_ARM-atf/lib/el3_runtime/aarch64/ |
| H A D | context.S | 549 orr x29, x29, #SCTLR_M_BIT
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| /rk3399_ARM-atf/include/arch/aarch32/ |
| H A D | arch.h | 178 #define SCTLR_M_BIT (U(1) << 0) macro
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| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | arch_helpers.h | 1003 assert((read_sctlr_el1() & SCTLR_M_BIT) != 0ULL); \
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| H A D | arch.h | 615 #define SCTLR_M_BIT (ULL(1) << 0) macro
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