Merge "fix(cm): deprecate use of NS_TIMER_SWITCH" into integration

fix(cm): deprecate use of NS_TIMER_SWITCH

On AArch64, secure world has it's own EL3 physical timer registers
accessible to secure EL1 in absence of S-EL2. With S-EL2 there is
virtualized view availa

fix(cm): deprecate use of NS_TIMER_SWITCH

On AArch64, secure world has it's own EL3 physical timer registers
accessible to secure EL1 in absence of S-EL2. With S-EL2 there is
virtualized view available for EL1 timer registers. So it is
unreasonable for secure world to use non-secure EL1 physical timer
registers. Moreover, the non-secure operating system (Linux in our case)
relies heavily on these EL1 physical timer registers for scheduling
decisions. If NS_TIMER_SWITCH is enabled, it simply breaks the preemption
model of the non-secure world by disabling non-secure timer interrupts
leading to RCU stalls being observed on long running secure world tasks.

The only arch timer register which will benefit from context management
is cntkctl_el1: Counter-timer Kernel Control Register. This enables the
secure and non-secure worlds to independently control accesses to EL0
for counter-timer registers. This is something that OP-TEE uses to
enable ftrace feature for Trusted Applications and SPM_MM uses for EL0
access as well.

Lets enable context management of cntkctl_el1 by default and deprecate
conditional context management of non-secure EL1 physical timer
registers for whom there isn't any upstream user. With that deprecate
this NS_TIMER_SWITCH build option which just adds confusion for the
platform maintainers. It will be eventually dropped following
deprecation policy of TF-A.

Reported-by: Stauffer Thomas MTANA <thomas.stauffer@mt.com>
Reported-by: Andrew Davis <afd@ti.com>
Change-Id: Ifb3a919dc0bf8c05c38895352de5fe94b4f4387e
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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Merge "fix(el3-spmc): update event log related include" into integration

fix(el3-spmc): update event log related include

This header provides APIs for managing an event log in a transfer list.
It was made part of LibTL, and removed in (b67e984) when we moved to
using Lib

fix(el3-spmc): update event log related include

This header provides APIs for managing an event log in a transfer list.
It was made part of LibTL, and removed in (b67e984) when we moved to
using LibEventLog as a submodule. This was missed during that update.

Change-Id: I279e23b25db40c04e9f2aae23e10ebddfe99419c
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topics "refactor_stmm", "stmm_crb_area", "stmm_with_xferlist" into integration

* changes:
feat(fvp): organize fvp_stmm_manifest.dts
feat(juno): add pseudo CRB area
feat(fvp)

Merge changes from topics "refactor_stmm", "stmm_crb_area", "stmm_with_xferlist" into integration

* changes:
feat(fvp): organize fvp_stmm_manifest.dts
feat(juno): add pseudo CRB area
feat(fvp): add pseudo CRB area
feat(arm): add pseudo CRB area
feat(juno): increase xtable for pseudo CRB
feat(fvp): increase xtable for pseudo CRB for SPMC_AT_EL3
feat(el3-spmc): deliver TPM event log via hob list
feat(el3-spmc): get sp_manifest via xferlist
feat(fvp): tos_fw_config with transfer list
feat(arm): load tos_fw_cfg using xferlist in SPMC_AT_EL3
feat(fvp): increase secure partition's table mapping count
feat(fvp): increase bl2 mmap tables for handoff

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feat(el3-spmc): deliver TPM event log via hob list

Add MM_TPM_EVENT_LOG hob type and deliver tpm meaured event logs
passed via secure transfer list to secure partition with hob list in
SPMC_AT_EL3.

feat(el3-spmc): deliver TPM event log via hob list

Add MM_TPM_EVENT_LOG hob type and deliver tpm meaured event logs
passed via secure transfer list to secure partition with hob list in
SPMC_AT_EL3.

So that secure partition could get the meausred event log by TF-A.

Change-Id: I14f7f8cb8f8f54e07a13f40748ca551bcd265a51
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(el3-spmc): get sp_manifest via xferlist

Since commit a852fa1d594f
("feat(arm): support boot info handoff and event log"),
the arg0 doesn't includes TOS_FW_CONFIG fdt but HW_CONFIG fdt is passed

feat(el3-spmc): get sp_manifest via xferlist

Since commit a852fa1d594f
("feat(arm): support boot info handoff and event log"),
the arg0 doesn't includes TOS_FW_CONFIG fdt but HW_CONFIG fdt is passed
via arg0 when SPMC_AT_EL3 build with TRANSFER_LIST option.

To resolve this, get TOS_FW_CONFIG (sp manifest) properly saved in
passed transfer list which saved with DT_FFA_MANIFEST tag.

Since delivered transfer list memory area is mapped
when BL31 is initialized, omit the mapping the manifest code
while initialize secure partition by spmc.

Change-Id: I3e02ca749a2b1828b171826a3829170001078d71
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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Merge changes from topic "hob_creation_in_tf_a" into integration

* changes:
feat(el3_spmc): ffa error handling in direct msg
feat(ff-a): support FFA_MSG_SEND_DIRECT_REQ2/RESP2
feat(ff-a): add

Merge changes from topic "hob_creation_in_tf_a" into integration

* changes:
feat(el3_spmc): ffa error handling in direct msg
feat(ff-a): support FFA_MSG_SEND_DIRECT_REQ2/RESP2
feat(ff-a): add FFA_MEM_PERM_GET/SET_SMC64
feat(el3-spmc): support Hob list to boot S-EL0 SP
feat(synquacer): add support Hob creation
fix(fvp): exclude extend memory map TZC regions
feat(fvp): add StandaloneMm manifest in fvp
feat(spm): use xfer list with Hob list in SPM_MM

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feat(el3-spmc): support Hob list to boot S-EL0 SP

The EDKII/StandaloneMm module runs as a S-EL0 partition
on top of the EL3 FF-A SPMC.

In the past the StandaloneMm partition received its boot infor

feat(el3-spmc): support Hob list to boot S-EL0 SP

The EDKII/StandaloneMm module runs as a S-EL0 partition
on top of the EL3 FF-A SPMC.

In the past the StandaloneMm partition received its boot information through
the use of a device tree (DT) passed through the FF-A boot protocol.
The StandaloneMm itself converted the DT into a HOB.

To better match the UEFI PI spec,
the EL3 SPMC must now produce the HOB including the PHIT
(Phase Handoff Information Table) as first item in the HOB list.
The SPMC then passes the HOB through the FF-A boot protocol for
the StandaloneMm consumption.

This discards the use of a DT between the SPMC and
the StandaloneMm partition.

Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: I22fb02c710169bd5a5ba1d1f60dce977a5a59ab6

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Merge "fix(el3-spmc): use write_el1_ctx_timer() macro to set cntkctl_el1 value" into integration

fix(el3-spmc): use write_el1_ctx_timer() macro to set cntkctl_el1 value

commit 42e35d2f8c0e
("refactor(cm): convert el1 ctx assembly offset entries to c structure")
moves cntkctl_el1 register from e

fix(el3-spmc): use write_el1_ctx_timer() macro to set cntkctl_el1 value

commit 42e35d2f8c0e
("refactor(cm): convert el1 ctx assembly offset entries to c structure")
moves cntkctl_el1 register from el1_sysregs_t's common to arch_timer
structure.
To set cntkctl_el1, it should use write_el1_ctx_timer() instead of
write_el1_ctx_common() otherwise, build failed.

Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Ifa1ca6e056fa95bd07598d20705856e208670808

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Merge "chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code" into integration

chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code

SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to wr

chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code

SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to write and read into these context entries, looks
repetitive and is invoked at most places.
This section is refactored to bring them under a static procedure,
keeping the code neat and easier to maintain.

Change-Id: Ib0d8c51bee09e1600c5baaa7f9745083dca9fee1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge changes from topic "jc/refact_el1_ctx" into integration

* changes:
refactor(cm): convert el1-ctx assembly offset entries to c structure
feat(cm): add explicit context entries for ERRATA_SP

Merge changes from topic "jc/refact_el1_ctx" into integration

* changes:
refactor(cm): convert el1-ctx assembly offset entries to c structure
feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

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refactor(cm): convert el1-ctx assembly offset entries to c structure

Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory alloca

refactor(cm): convert el1-ctx assembly offset entries to c structure

Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory allocation
for platforms, that don't enable/support all the architectural
features at once.

Similar to the el2 context optimization commit-"d6af234" this patch
further improves this section by converting the assembly context-offset
entries into a c structure. It relies on garbage collection of the
linker removing unreferenced structures from memory, as well as aiding
in readability and future maintenance. Additionally, it eliminates
the #ifs usage in 'context_mgmt.c' source file.

Change-Id: If6075931cec994bc89231241337eccc7042c5ede
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
rest

feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
restoring EL1 regs "SCTLR_EL1 and TCR_EL1" registers at all times.

* This prevents the mechanism of decoupling EL1 and EL2 registers,
as EL3 firmware shouldn't be handling both simultaneously.

* Depending on the build configuration either EL1 or EL2 context
structures need to included, which would result in saving a good
amount of context memory.

* In order to achieve this it's essential to have explicit context
entries for registers supporting "ERRATA_SPECULATIVE_AT".

* This patch adds two context entries under "errata_speculative_at"
structure to assist this errata and thereby allows decoupling
EL1 and EL2 context structures.

Change-Id: Ia50626eea8fb64899a2e2d81622adbe07fe77d65
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge changes from topic "ns/spmc_at_el3" into integration

* changes:
feat(rdn2): add dts for secure partition
feat(el3-spmc): synchronize access to the s-el0 sp context
feat(el3-spmc): add su

Merge changes from topic "ns/spmc_at_el3" into integration

* changes:
feat(rdn2): add dts for secure partition
feat(el3-spmc): synchronize access to the s-el0 sp context
feat(el3-spmc): add support to map S-EL0 SP device regions
feat(el3-spmc): add support to map S-EL0 SP memory regions
feat(el3-spmc): add support for FFA_MEM_PERM_GET and SET ABIs
feat(el3-spmc): add support to setup S-EL0 context

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feat(el3-spmc): add support to map S-EL0 SP device regions

Add the support to parse SP manifest to get device regions, create xlat
table entries for the SP.

SP running at SEL-0 does not have enough

feat(el3-spmc): add support to map S-EL0 SP device regions

Add the support to parse SP manifest to get device regions, create xlat
table entries for the SP.

SP running at SEL-0 does not have enough privilege to map the regions
itself.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I600f51ee62a33443fe7f1c4e007cc6c5ab45222f

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feat(el3-spmc): add support to map S-EL0 SP memory regions

Add the support to parse SP manifest to get memory regions, create xlat
tables and then program it in TTBR0.

SP manifest contains the info

feat(el3-spmc): add support to map S-EL0 SP memory regions

Add the support to parse SP manifest to get memory regions, create xlat
tables and then program it in TTBR0.

SP manifest contains the info on memory map regions that are needed by
the SP. These regions needs to be mapped as SP running at S-EL0 does not
have privilege to do it.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I0cad36e5c43f8a68c94887ff2bd798933a26be27

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feat(el3-spmc): add support to setup S-EL0 context

Add support to setup S-EL0 context by setting up the following

S-EL1 shim exception handlers: This is a trampoline between S-EL0 and

feat(el3-spmc): add support to setup S-EL0 context

Add support to setup S-EL0 context by setting up the following

S-EL1 shim exception handlers: This is a trampoline between S-EL0 and
monitor running at EL3 and is used to
handle or forward exceptions from S-EL0.

Boot Info region: This region holds the boot protocol data that is
passed between SPMC and SP.

Setup system registers: Setup sctlr_el1, vbar_el1, cntkctl_el1,
ctx_cpacr_el1(enable fp and smid), spsr and
sp_el0

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I82d21fcd95529f235bee8bf838d36a2ac519bb0a

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Merge changes I1bfa797e,I0ec7a70e into integration

* changes:
fix(tree): correct some typos
fix(rockchip): use semicolon instead of comma

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373

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Merge changes from topic "ffa_el3_spmc" into integration

* changes:
feat(fvp): add plat hook for memory transactions
feat(spmc): enable handling of the NS bit
feat(spmc): add support for v1.1

Merge changes from topic "ffa_el3_spmc" into integration

* changes:
feat(fvp): add plat hook for memory transactions
feat(spmc): enable handling of the NS bit
feat(spmc): add support for v1.1 FF-A memory data structures
feat(spmc/mem): prevent duplicated sharing of memory regions
feat(spmc/mem): support multiple endpoints in memory transactions
feat(spmc): add support for v1.1 FF-A boot protocol
feat(plat/fvp): introduce accessor function to obtain datastore
feat(spmc/mem): add FF-A memory management code

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feat(spmc): add support for v1.1 FF-A boot protocol

A partition can request the use of the FF-A boot protocol via
an entry in its manifest along with the register (0-3)
that should be populated with

feat(spmc): add support for v1.1 FF-A boot protocol

A partition can request the use of the FF-A boot protocol via
an entry in its manifest along with the register (0-3)
that should be populated with a pointer to a data structure
containing boot related information. Currently the boot
information consists of an allocated memory region
containing the SP's manifest, allowing it to map and parse
any extra information as required.

This implementation only supports the v1.1 data structures
and will return an error if a v1.0 client requests the usage
of the protocol.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I67692553a90a7e7d94c64fe275edd247b512efca

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Merge changes from topic "ffa_el3_spmc" into integration

* changes:
feat(spmc): enable the SPMC to pass the linear core ID in a register
feat(spmc): add FFA_RX_RELEASE handler
feat(spmc): add

Merge changes from topic "ffa_el3_spmc" into integration

* changes:
feat(spmc): enable the SPMC to pass the linear core ID in a register
feat(spmc): add FFA_RX_RELEASE handler
feat(spmc): add FFA_RUN handler
feat(spmc): support FFA_ID_GET ABI
feat(spmc): add FFA_FEATURES handler
feat(spmc): add FFA_PARTITION_INFO_GET handler
feat(spmc): enable handling FF-A RX/TX Mapping ABIs
docs(maintainers): introduce SPMC maintainer section

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