12c3a1078SDimitris Papastamos/* 2*4c700c15SGovindraj Raja * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. 32c3a1078SDimitris Papastamos * 42c3a1078SDimitris Papastamos * SPDX-License-Identifier: BSD-3-Clause 52c3a1078SDimitris Papastamos */ 62c3a1078SDimitris Papastamos 72c3a1078SDimitris Papastamos#include <arch.h> 82c3a1078SDimitris Papastamos#include <asm_macros.S> 92c3a1078SDimitris Papastamos#include <context.h> 1009d40e0eSAntonio Nino Diaz#include <services/arm_arch_svc.h> 112c3a1078SDimitris Papastamos 122c3a1078SDimitris Papastamos .globl wa_cve_2017_5715_mmu_vbar 132c3a1078SDimitris Papastamos 142c3a1078SDimitris Papastamos#define ESR_EL3_A64_SMC0 0x5e000000 152b915366SDimitris Papastamos#define ESR_EL3_A32_SMC0 0x4e000000 162c3a1078SDimitris Papastamos 172c3a1078SDimitris Papastamosvector_base wa_cve_2017_5715_mmu_vbar 182c3a1078SDimitris Papastamos 192b915366SDimitris Papastamos .macro apply_cve_2017_5715_wa _is_sync_exception _esr_el3_val 202c3a1078SDimitris Papastamos stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 212c3a1078SDimitris Papastamos mrs x1, sctlr_el3 222c3a1078SDimitris Papastamos /* Disable MMU */ 232c3a1078SDimitris Papastamos bic x1, x1, #SCTLR_M_BIT 242c3a1078SDimitris Papastamos msr sctlr_el3, x1 252c3a1078SDimitris Papastamos isb 262c3a1078SDimitris Papastamos /* Enable MMU */ 272c3a1078SDimitris Papastamos orr x1, x1, #SCTLR_M_BIT 282c3a1078SDimitris Papastamos msr sctlr_el3, x1 292c3a1078SDimitris Papastamos /* 302c3a1078SDimitris Papastamos * Defer ISB to avoid synchronizing twice in case we hit 312c3a1078SDimitris Papastamos * the workaround SMC call which will implicitly synchronize 322c3a1078SDimitris Papastamos * because of the ERET instruction. 332c3a1078SDimitris Papastamos */ 342c3a1078SDimitris Papastamos 352c3a1078SDimitris Papastamos /* 362b915366SDimitris Papastamos * Ensure SMC is coming from A64/A32 state on #0 379b2510b6SBipin Ravi * with W0 = SMCCC_ARCH_WORKAROUND_1 or W0 = SMCCC_ARCH_WORKAROUND_3 382c3a1078SDimitris Papastamos * 392c3a1078SDimitris Papastamos * This sequence evaluates as: 409b2510b6SBipin Ravi * (W0==SMCCC_ARCH_WORKAROUND_1) || (W0==SMCCC_ARCH_WORKAROUND_3) ? 419b2510b6SBipin Ravi * (ESR_EL3==SMC#0) : (NE) 422c3a1078SDimitris Papastamos * allowing use of a single branch operation 432c3a1078SDimitris Papastamos */ 442c3a1078SDimitris Papastamos .if \_is_sync_exception 452c3a1078SDimitris Papastamos orr w1, wzr, #SMCCC_ARCH_WORKAROUND_1 462c3a1078SDimitris Papastamos cmp w0, w1 479b2510b6SBipin Ravi orr w1, wzr, #SMCCC_ARCH_WORKAROUND_3 489b2510b6SBipin Ravi ccmp w0, w1, #4, ne 492c3a1078SDimitris Papastamos mrs x0, esr_el3 502b915366SDimitris Papastamos mov_imm w1, \_esr_el3_val 512c3a1078SDimitris Papastamos ccmp w0, w1, #0, eq 522c3a1078SDimitris Papastamos /* Static predictor will predict a fall through */ 532c3a1078SDimitris Papastamos bne 1f 54f461fe34SAnthony Steinhauser exception_return 552c3a1078SDimitris Papastamos1: 562c3a1078SDimitris Papastamos .endif 572c3a1078SDimitris Papastamos 582c3a1078SDimitris Papastamos /* 592c3a1078SDimitris Papastamos * Synchronize now to enable the MMU. This is required 602c3a1078SDimitris Papastamos * to ensure the load pair below reads the data stored earlier. 612c3a1078SDimitris Papastamos */ 622c3a1078SDimitris Papastamos isb 632c3a1078SDimitris Papastamos ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 642c3a1078SDimitris Papastamos .endm 652c3a1078SDimitris Papastamos 662c3a1078SDimitris Papastamos /* --------------------------------------------------------------------- 672c3a1078SDimitris Papastamos * Current EL with SP_EL0 : 0x0 - 0x200 682c3a1078SDimitris Papastamos * --------------------------------------------------------------------- 692c3a1078SDimitris Papastamos */ 702c3a1078SDimitris Papastamosvector_entry mmu_sync_exception_sp_el0 712c3a1078SDimitris Papastamos b sync_exception_sp_el0 72a9203edaSRoberto Vargasend_vector_entry mmu_sync_exception_sp_el0 732c3a1078SDimitris Papastamos 742c3a1078SDimitris Papastamosvector_entry mmu_irq_sp_el0 752c3a1078SDimitris Papastamos b irq_sp_el0 76a9203edaSRoberto Vargasend_vector_entry mmu_irq_sp_el0 772c3a1078SDimitris Papastamos 782c3a1078SDimitris Papastamosvector_entry mmu_fiq_sp_el0 792c3a1078SDimitris Papastamos b fiq_sp_el0 80a9203edaSRoberto Vargasend_vector_entry mmu_fiq_sp_el0 812c3a1078SDimitris Papastamos 822c3a1078SDimitris Papastamosvector_entry mmu_serror_sp_el0 832c3a1078SDimitris Papastamos b serror_sp_el0 84a9203edaSRoberto Vargasend_vector_entry mmu_serror_sp_el0 852c3a1078SDimitris Papastamos 862c3a1078SDimitris Papastamos /* --------------------------------------------------------------------- 872c3a1078SDimitris Papastamos * Current EL with SP_ELx: 0x200 - 0x400 882c3a1078SDimitris Papastamos * --------------------------------------------------------------------- 892c3a1078SDimitris Papastamos */ 902c3a1078SDimitris Papastamosvector_entry mmu_sync_exception_sp_elx 912c3a1078SDimitris Papastamos b sync_exception_sp_elx 92a9203edaSRoberto Vargasend_vector_entry mmu_sync_exception_sp_elx 932c3a1078SDimitris Papastamos 942c3a1078SDimitris Papastamosvector_entry mmu_irq_sp_elx 952c3a1078SDimitris Papastamos b irq_sp_elx 96a9203edaSRoberto Vargasend_vector_entry mmu_irq_sp_elx 972c3a1078SDimitris Papastamos 982c3a1078SDimitris Papastamosvector_entry mmu_fiq_sp_elx 992c3a1078SDimitris Papastamos b fiq_sp_elx 100a9203edaSRoberto Vargasend_vector_entry mmu_fiq_sp_elx 1012c3a1078SDimitris Papastamos 1022c3a1078SDimitris Papastamosvector_entry mmu_serror_sp_elx 1032c3a1078SDimitris Papastamos b serror_sp_elx 104a9203edaSRoberto Vargasend_vector_entry mmu_serror_sp_elx 1052c3a1078SDimitris Papastamos 1062c3a1078SDimitris Papastamos /* --------------------------------------------------------------------- 1072c3a1078SDimitris Papastamos * Lower EL using AArch64 : 0x400 - 0x600 1082c3a1078SDimitris Papastamos * --------------------------------------------------------------------- 1092c3a1078SDimitris Papastamos */ 1102c3a1078SDimitris Papastamosvector_entry mmu_sync_exception_aarch64 1112b915366SDimitris Papastamos apply_cve_2017_5715_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A64_SMC0 1122c3a1078SDimitris Papastamos b sync_exception_aarch64 113a9203edaSRoberto Vargasend_vector_entry mmu_sync_exception_aarch64 1142c3a1078SDimitris Papastamos 1152c3a1078SDimitris Papastamosvector_entry mmu_irq_aarch64 1162b915366SDimitris Papastamos apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0 1172c3a1078SDimitris Papastamos b irq_aarch64 118a9203edaSRoberto Vargasend_vector_entry mmu_irq_aarch64 1192c3a1078SDimitris Papastamos 1202c3a1078SDimitris Papastamosvector_entry mmu_fiq_aarch64 1212b915366SDimitris Papastamos apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0 1222c3a1078SDimitris Papastamos b fiq_aarch64 123a9203edaSRoberto Vargasend_vector_entry mmu_fiq_aarch64 1242c3a1078SDimitris Papastamos 1252c3a1078SDimitris Papastamosvector_entry mmu_serror_aarch64 1262b915366SDimitris Papastamos apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0 1272c3a1078SDimitris Papastamos b serror_aarch64 128a9203edaSRoberto Vargasend_vector_entry mmu_serror_aarch64 1292c3a1078SDimitris Papastamos 1302c3a1078SDimitris Papastamos /* --------------------------------------------------------------------- 1312c3a1078SDimitris Papastamos * Lower EL using AArch32 : 0x600 - 0x800 1322c3a1078SDimitris Papastamos * --------------------------------------------------------------------- 1332c3a1078SDimitris Papastamos */ 1342c3a1078SDimitris Papastamosvector_entry mmu_sync_exception_aarch32 1352b915366SDimitris Papastamos apply_cve_2017_5715_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A32_SMC0 1362c3a1078SDimitris Papastamos b sync_exception_aarch32 137a9203edaSRoberto Vargasend_vector_entry mmu_sync_exception_aarch32 1382c3a1078SDimitris Papastamos 1392c3a1078SDimitris Papastamosvector_entry mmu_irq_aarch32 1402b915366SDimitris Papastamos apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0 1412c3a1078SDimitris Papastamos b irq_aarch32 142a9203edaSRoberto Vargasend_vector_entry mmu_irq_aarch32 1432c3a1078SDimitris Papastamos 1442c3a1078SDimitris Papastamosvector_entry mmu_fiq_aarch32 1452b915366SDimitris Papastamos apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0 1462c3a1078SDimitris Papastamos b fiq_aarch32 147a9203edaSRoberto Vargasend_vector_entry mmu_fiq_aarch32 1482c3a1078SDimitris Papastamos 1492c3a1078SDimitris Papastamosvector_entry mmu_serror_aarch32 1502b915366SDimitris Papastamos apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0 1512c3a1078SDimitris Papastamos b serror_aarch32 152a9203edaSRoberto Vargasend_vector_entry mmu_serror_aarch32 153