| #
4bd8c929 |
| 09-May-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I1bfa797e,I0ec7a70e into integration
* changes:
fix(tree): correct some typos
fix(rockchip): use semicolon instead of comma
|
| #
1b491eea |
| 13-Feb-2023 |
Elyes Haouas <ehaouas@noos.fr> |
fix(tree): correct some typos
found using codespell (https://github.com/codespell-project/codespell).
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6
fix(tree): correct some typos
found using codespell (https://github.com/codespell-project/codespell).
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
show more ...
|
| #
521d4fe6 |
| 13-Mar-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "style: remove useless trailing semicolon and line continuations" into integration
|
| #
9a90d720 |
| 13-Feb-2023 |
Elyes Haouas <ehaouas@noos.fr> |
style: remove useless trailing semicolon and line continuations
found using checkpatch.pl[1]
[1]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/lint/checkpatch.pl
S
style: remove useless trailing semicolon and line continuations
found using checkpatch.pl[1]
[1]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/lint/checkpatch.pl
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I7957c9694300fefb85d11f7819c43af95271f14c
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|
| #
338dbe2f |
| 22-Feb-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I51c13c52,I3358c51e into integration
* changes:
build: always prefix section names with `.`
build: communicate correct page size to linker
|
| #
da04341e |
| 14-Feb-2023 |
Chris Kay <chris.kay@arm.com> |
build: always prefix section names with `.`
Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section name
build: always prefix section names with `.`
Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be
difficult to select in linker scripts when there is a lack of a
delimiter.
This change introduces the period prefix to all specialized section
names.
BREAKING-CHANGE: All input and output linker section names have been
prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.
Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c
Signed-off-by: Chris Kay <chris.kay@arm.com>
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| #
28e2daa9 |
| 03-Aug-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Aarch32 xlat_tables lib: Fix MISRA-2012 defects" into integration
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| #
77a38690 |
| 28-Jul-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Aarch32 xlat_tables lib: Fix MISRA-2012 defects
This patch fixes violation of Rules 2.1, 7.3, 10.1,
10.4, 12.1, 14.3, 14.4, 17.7, 20.9 reported by
MISRA-2012 scan and adds braces for conditional
sta
Aarch32 xlat_tables lib: Fix MISRA-2012 defects
This patch fixes violation of Rules 2.1, 7.3, 10.1,
10.4, 12.1, 14.3, 14.4, 17.7, 20.9 reported by
MISRA-2012 scan and adds braces for conditional
statements according to the TF-A coding style.
Change-Id: Ib2463601fb43d955c3d901102b6dceaaad6614f3
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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| #
b27280a8 |
| 15-Nov-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "Coding guideline suggest not to use unsigned long" into integration
|
| #
9afe8cdc |
| 03-Sep-2019 |
Deepika Bhavnani <deepika.bhavnani@arm.com> |
Coding guideline suggest not to use unsigned long
`unsigned long` should be replaced to
1. `unsigned int` or `unsigned long long` - If fixed,
based on the architecture AArch32 or AArch64
2. `u_regis
Coding guideline suggest not to use unsigned long
`unsigned long` should be replaced to
1. `unsigned int` or `unsigned long long` - If fixed,
based on the architecture AArch32 or AArch64
2. `u_register_t` - If it is supposed to be 32-bit
wide in AArch32 and 64-bit wide in AArch64.
Translation descriptors are always 32-bit wide, here
`uint32_t` is used to describe the `exact size` of
translation descriptors instead of `unsigned int` which
guarantees minimum 32-bits
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I6a2af2e8b3c71170e2634044e0b887f07a41677e
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| #
a8ab58e9 |
| 13-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge changes from topic "jc/coverity-fixes" into integration
* changes:
Fix Coverity #261967, Infinite loop
Fix Coverity #343017, Missing unlock
Fix Coverity #343008, Side affect in assertion
Merge changes from topic "jc/coverity-fixes" into integration
* changes:
Fix Coverity #261967, Infinite loop
Fix Coverity #343017, Missing unlock
Fix Coverity #343008, Side affect in assertion
Fix Coverity #342970, Uninitialized scalar variable
show more ...
|
| #
4249e8b9 |
| 23-Jul-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Fix Coverity #343008, Side affect in assertion
This patch simply splits off the increment of next_xlat into a separate
statement to ensure consistent behaviour if the assert was to ever be
removed.
Fix Coverity #343008, Side affect in assertion
This patch simply splits off the increment of next_xlat into a separate
statement to ensure consistent behaviour if the assert was to ever be
removed.
Change-Id: I827f601ccea55f4da9442048419c9b8cc0c5d22e
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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|
| #
d0d0f171 |
| 16-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "jc/shift-overflow" into integration
* changes:
Enable -Wshift-overflow=2 to check for undefined shift behavior
Update base code to not rely on undefined overflow behavi
Merge changes from topic "jc/shift-overflow" into integration
* changes:
Enable -Wshift-overflow=2 to check for undefined shift behavior
Update base code to not rely on undefined overflow behaviour
Update hisilicon drivers to not rely on undefined overflow behaviour
Update synopsys drivers to not rely on undefined overflow behaviour
Update imx platform to not rely on undefined overflow behaviour
Update mediatek platform to not rely on undefined overflow behaviour
Update layerscape platform to not rely on undefined overflow behaviour
Update intel platform to not rely on undefined overflow behaviour
Update rockchip platform to not rely on undefined overflow behaviour
Update renesas platform to not rely on undefined overflow behaviour
Update meson platform to not rely on undefined overflow behaviour
Update marvell platform to not rely on undefined overflow behaviour
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| #
3e43121e |
| 03-Jul-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Update base code to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.
Change-Id
Update base code to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.
Change-Id: Iddd6f38139a4c6e500468b4fc48d04e0939f574e
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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| #
5ba32a76 |
| 21-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1828 from uarif1/master
Introduce Versatile Express FVP platform to arm-trusted-firmware.
|
| #
c9fe6fed |
| 24-Oct-2017 |
Etienne Carriere <etienne.carriere@linaro.org> |
ARMv7: support non-LPAE mapping (not xlat_v2)
Support 32bit descriptor MMU table. This is required by ARMv7
architectures that do not support the Large Page Address Extensions.
nonlpae_tables.c sou
ARMv7: support non-LPAE mapping (not xlat_v2)
Support 32bit descriptor MMU table. This is required by ARMv7
architectures that do not support the Large Page Address Extensions.
nonlpae_tables.c source file is dumped from the OP-TEE project:
core_mmu_armv7.c and related header files.
Change-Id: If912d66c374290c49c5a1211ce4c5c27b2d7dc60
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Usama Arif <usama.arif@arm.com>
show more ...
|