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Searched refs:EMI_MPU_BASE (Results 1 – 11 of 11) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/emi_mpu/
H A Demi_mpu.h18 #define EMI_MPU_CTRL (EMI_MPU_BASE + 0x0000)
53 #define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100)
54 #define EMI_MPU_SA1 (EMI_MPU_BASE + 0x104)
55 #define EMI_MPU_SA2 (EMI_MPU_BASE + 0x108)
56 #define EMI_MPU_SA3 (EMI_MPU_BASE + 0x10C)
57 #define EMI_MPU_SA4 (EMI_MPU_BASE + 0x110)
58 #define EMI_MPU_SA5 (EMI_MPU_BASE + 0x114)
59 #define EMI_MPU_SA6 (EMI_MPU_BASE + 0x118)
60 #define EMI_MPU_SA7 (EMI_MPU_BASE + 0x11C)
62 #define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200)
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/emi_mpu/mt8188/
H A Demi_mpu_priv.h12 #define EMI_MPU_CTRL (EMI_MPU_BASE + 0x000)
13 #define EMI_MPU_DBG (EMI_MPU_BASE + 0x004)
14 #define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100)
15 #define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200)
18 #define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300)
20 #define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800)
22 #define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900)
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/emi_mpu/
H A Demi_mpu.h14 #define EMI_MPU_CTRL (EMI_MPU_BASE + 0x000)
15 #define EMI_MPU_DBG (EMI_MPU_BASE + 0x004)
16 #define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100)
17 #define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200)
20 #define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300)
22 #define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800)
24 #define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900)
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/emi_mpu/
H A Demi_mpu.h14 #define EMI_MPU_CTRL (EMI_MPU_BASE + 0x000)
15 #define EMI_MPU_DBG (EMI_MPU_BASE + 0x004)
16 #define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100)
17 #define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200)
20 #define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300)
22 #define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800)
24 #define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900)
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/emi_mpu/
H A Demi_mpu.h18 #define EMI_MPU_CTRL (EMI_MPU_BASE + 0x0000)
41 #define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100)
42 #define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200)
46 #define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300)
50 #define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800)
52 #define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900)
/rk3399_ARM-atf/plat/mediatek/mt8192/include/
H A Dplatform_def.h51 #define EMI_MPU_BASE (IO_PHYS + 0x00226000) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/include/
H A Dplatform_def.h72 #define EMI_MPU_BASE (IO_PHYS + 0x0021B000) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/include/
H A Dplatform_def.h83 #define EMI_MPU_BASE (IO_PHYS + 0x00226000) macro
/rk3399_ARM-atf/plat/mediatek/mt8188/include/
H A Dplatform_def.h189 #define EMI_MPU_BASE (IO_PHYS + 0x00226000) macro
/rk3399_ARM-atf/plat/mediatek/mt8196/include/
H A Dplatform_def.h218 #define EMI_MPU_BASE (IO_PHYS + 0x00428000) macro
/rk3399_ARM-atf/plat/mediatek/mt8183/include/
H A Dplatform_def.h29 #define EMI_MPU_BASE (IO_PHYS + 0x226000) macro