1*42f2fa82SXi Chen /* 2*42f2fa82SXi Chen * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*42f2fa82SXi Chen * 4*42f2fa82SXi Chen * SPDX-License-Identifier: BSD-3-Clause 5*42f2fa82SXi Chen */ 6*42f2fa82SXi Chen 7*42f2fa82SXi Chen #ifndef EMI_MPU_H 8*42f2fa82SXi Chen #define EMI_MPU_H 9*42f2fa82SXi Chen 10*42f2fa82SXi Chen #include <platform_def.h> 11*42f2fa82SXi Chen 12*42f2fa82SXi Chen #define EMI_MPUP (EMI_BASE + 0x01D8) 13*42f2fa82SXi Chen #define EMI_MPUQ (EMI_BASE + 0x01E0) 14*42f2fa82SXi Chen #define EMI_MPUR (EMI_BASE + 0x01E8) 15*42f2fa82SXi Chen #define EMI_MPUS (EMI_BASE + 0x01F0) 16*42f2fa82SXi Chen #define EMI_MPUT (EMI_BASE + 0x01F8) 17*42f2fa82SXi Chen #define EMI_MPUY (EMI_BASE + 0x0220) 18*42f2fa82SXi Chen #define EMI_MPU_CTRL (EMI_MPU_BASE + 0x0000) 19*42f2fa82SXi Chen #define EMI_MPUD0_ST (EMI_BASE + 0x0160) 20*42f2fa82SXi Chen #define EMI_MPUD1_ST (EMI_BASE + 0x0164) 21*42f2fa82SXi Chen #define EMI_MPUD2_ST (EMI_BASE + 0x0168) 22*42f2fa82SXi Chen #define EMI_MPUD3_ST (EMI_BASE + 0x016C) 23*42f2fa82SXi Chen #define EMI_MPUD0_ST2 (EMI_BASE + 0x0200) 24*42f2fa82SXi Chen #define EMI_MPUD1_ST2 (EMI_BASE + 0x0204) 25*42f2fa82SXi Chen #define EMI_MPUD2_ST2 (EMI_BASE + 0x0208) 26*42f2fa82SXi Chen #define EMI_MPUD3_ST2 (EMI_BASE + 0x020C) 27*42f2fa82SXi Chen 28*42f2fa82SXi Chen #define EMI_PHY_OFFSET (0x40000000UL) 29*42f2fa82SXi Chen 30*42f2fa82SXi Chen #define NO_PROT (0) 31*42f2fa82SXi Chen #define SEC_RW (1) 32*42f2fa82SXi Chen #define SEC_RW_NSEC_R (2) 33*42f2fa82SXi Chen #define SEC_RW_NSEC_W (3) 34*42f2fa82SXi Chen #define SEC_R_NSEC_R (4) 35*42f2fa82SXi Chen #define FORBIDDEN (5) 36*42f2fa82SXi Chen #define SEC_R_NSEC_RW (6) 37*42f2fa82SXi Chen 38*42f2fa82SXi Chen #define SECURE_OS_MPU_REGION_ID (0) 39*42f2fa82SXi Chen #define ATF_MPU_REGION_ID (1) 40*42f2fa82SXi Chen 41*42f2fa82SXi Chen #define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100) 42*42f2fa82SXi Chen #define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200) 43*42f2fa82SXi Chen #define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region) * 4) 44*42f2fa82SXi Chen #define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region) * 4) 45*42f2fa82SXi Chen 46*42f2fa82SXi Chen #define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300) 47*42f2fa82SXi Chen #define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region) * 4 + \ 48*42f2fa82SXi Chen (dgroup) * 0x100) 49*42f2fa82SXi Chen 50*42f2fa82SXi Chen #define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800) 51*42f2fa82SXi Chen #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + domain * 4) 52*42f2fa82SXi Chen #define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900) 53*42f2fa82SXi Chen #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + domain * 4) 54*42f2fa82SXi Chen 55*42f2fa82SXi Chen #define EMI_MPU_DOMAIN_NUM 16 56*42f2fa82SXi Chen #define EMI_MPU_REGION_NUM 32 57*42f2fa82SXi Chen #define EMI_MPU_ALIGN_BITS 16 58*42f2fa82SXi Chen #define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS) 59*42f2fa82SXi Chen 60*42f2fa82SXi Chen #define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8) 61*42f2fa82SXi Chen 62*42f2fa82SXi Chen #if (EMI_MPU_DGROUP_NUM == 1) 63*42f2fa82SXi Chen #define SET_ACCESS_PERMISSION(apc_ary, lock, d7, d6, d5, d4, d3, d2, d1, d0) \ 64*42f2fa82SXi Chen do { \ 65*42f2fa82SXi Chen apc_ary[0] = 0; \ 66*42f2fa82SXi Chen apc_ary[0] = \ 67*42f2fa82SXi Chen (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) \ 68*42f2fa82SXi Chen | (((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) \ 69*42f2fa82SXi Chen | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) \ 70*42f2fa82SXi Chen | (((unsigned int) d1) << 3) | ((unsigned int) d0) \ 71*42f2fa82SXi Chen | (((unsigned int) lock) << 31); \ 72*42f2fa82SXi Chen } while (0) 73*42f2fa82SXi Chen #elif (EMI_MPU_DGROUP_NUM == 2) 74*42f2fa82SXi Chen #define SET_ACCESS_PERMISSION(apc_ary, lock, d15, d14, d13, d12, d11, d10, \ 75*42f2fa82SXi Chen d9, d8, d7, d6, d5, d4, d3, d2, d1, d0) \ 76*42f2fa82SXi Chen do { \ 77*42f2fa82SXi Chen apc_ary[1] = \ 78*42f2fa82SXi Chen (((unsigned int) d15) << 21) | (((unsigned int) d14) << 18) \ 79*42f2fa82SXi Chen | (((unsigned int) d13) << 15) | (((unsigned int) d12) << 12) \ 80*42f2fa82SXi Chen | (((unsigned int) d11) << 9) | (((unsigned int) d10) << 6) \ 81*42f2fa82SXi Chen | (((unsigned int) d9) << 3) | ((unsigned int) d8); \ 82*42f2fa82SXi Chen apc_ary[0] = \ 83*42f2fa82SXi Chen (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) \ 84*42f2fa82SXi Chen | (((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) \ 85*42f2fa82SXi Chen | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) \ 86*42f2fa82SXi Chen | (((unsigned int) d1) << 3) | ((unsigned int) d0) \ 87*42f2fa82SXi Chen | (((unsigned int) lock) << 31); \ 88*42f2fa82SXi Chen } while (0) 89*42f2fa82SXi Chen #endif 90*42f2fa82SXi Chen 91*42f2fa82SXi Chen struct emi_region_info_t { 92*42f2fa82SXi Chen unsigned long long start; 93*42f2fa82SXi Chen unsigned long long end; 94*42f2fa82SXi Chen unsigned int region; 95*42f2fa82SXi Chen unsigned long apc[EMI_MPU_DGROUP_NUM]; 96*42f2fa82SXi Chen }; 97*42f2fa82SXi Chen 98*42f2fa82SXi Chen void emi_mpu_init(void); 99*42f2fa82SXi Chen int emi_mpu_set_protection(struct emi_region_info_t *region_info); 100*42f2fa82SXi Chen void dump_emi_mpu_regions(void); 101*42f2fa82SXi Chen 102*42f2fa82SXi Chen #endif /* __EMI_MPU_H */ 103