| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | generic.S | 23 mov x0, #DCCISW
36 mov x0, #DCCISW
49 mov x0, #DCCISW
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| H A D | aem_generic.S | 32 mov x0, #DCCISW
48 mov x0, #DCCISW
57 mov x0, #DCCISW
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| H A D | cortex_a35.S | 51 mov x0, #DCCISW
69 mov x0, #DCCISW
82 mov x0, #DCCISW
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| H A D | qemu_max.S | 19 mov x0, #DCCISW
30 mov x0, #DCCISW
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| H A D | cortex_a73.S | 119 mov x0, #DCCISW
137 mov x0, #DCCISW
150 mov x0, #DCCISW
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| H A D | cortex_a53.S | 140 mov x0, #DCCISW
158 mov x0, #DCCISW
171 mov x0, #DCCISW
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| H A D | cortex_a72.S | 183 mov x0, #DCCISW
224 mov x0, #DCCISW
238 mov x0, #DCCISW
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| H A D | cortex_a57.S | 202 mov x0, #DCCISW
237 mov x0, #DCCISW
250 mov x0, #DCCISW
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| /rk3399_ARM-atf/drivers/renesas/rcar_gen5/pwrc/ |
| H A D | pwrc.c | 28 dcsw_op_all(DCCISW); in rcar_pwrc_suspend_to_ram()
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| /rk3399_ARM-atf/plat/arm/board/corstone1000/common/ |
| H A D | corstone1000_pm.c | 38 dcsw_op_all(DCCISW); in corstone1000_system_reset()
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| /rk3399_ARM-atf/plat/intel/soc/common/ |
| H A D | socfpga_psci.c | 209 dcsw_op_all(DCCISW); in socfpga_system_reset()
231 dcsw_op_all(DCCISW); in socfpga_system_reset2()
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| /rk3399_ARM-atf/plat/brcm/board/stingray/src/ |
| H A D | brcm_pm_ops.c | 231 dcsw_op_all(DCCISW); in brcm_scp_sys_shutdown()
258 dcsw_op_all(DCCISW); in brcm_scp_sys_reset()
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| /rk3399_ARM-atf/drivers/renesas/common/auth/ |
| H A D | auth_mod.c | 116 dcsw_op_all(DCCISW); in auth_mod_verify_img()
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| /rk3399_ARM-atf/lib/xlat_tables_v2/ |
| H A D | xlat_tables_context.c | 154 dcsw_op_all(DCCISW); in xlat_make_tables_readonly()
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| /rk3399_ARM-atf/lib/aarch32/ |
| H A D | cache_helpers.S | 155 stcopr r0, DCCISW
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| /rk3399_ARM-atf/plat/qti/qtiseclib/src/ |
| H A D | qtiseclib_cb_interface.c | 187 dcsw_op_all(DCCISW); in qtiseclib_cb_flush_dcache_all()
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| /rk3399_ARM-atf/plat/renesas/common/aarch64/ |
| H A D | plat_helpers.S | 182 mov x0, #DCCISW
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| /rk3399_ARM-atf/drivers/renesas/rcar_gen4/pwrc/ |
| H A D | pwrc.c | 440 dcsw_op_all(DCCISW); in rcar_pwrc_suspend_to_ram()
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| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | arch.h | 184 #define DCCISW U(0x1) macro
186 #define DCCSW DCCISW
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| /rk3399_ARM-atf/include/arch/aarch32/ |
| H A D | arch.h | 548 #define DCCISW p15, 0, c7, c14, 2 macro
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| /rk3399_ARM-atf/plat/renesas/rcar/ |
| H A D | bl2_plat_setup.c | 374 dcsw_op_all(DCCISW); in bl2_plat_flush_bl31_params()
|