1820756e9SSandrine Bailleux/* 2*89dba82dSBoyan Karatotev * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved. 3820756e9SSandrine Bailleux * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5820756e9SSandrine Bailleux */ 6820756e9SSandrine Bailleux 7820756e9SSandrine Bailleux#include <arch.h> 8820756e9SSandrine Bailleux#include <asm_macros.S> 909d40e0eSAntonio Nino Diaz#include <common/bl_common.h> 10820756e9SSandrine Bailleux#include <cortex_a35.h> 11820756e9SSandrine Bailleux#include <cpu_macros.S> 12820756e9SSandrine Bailleux#include <plat_macros.S> 13820756e9SSandrine Bailleux 14*89dba82dSBoyan Karatotevcpu_reset_prologue cortex_a35 15820756e9SSandrine Bailleux /* --------------------------------------------- 16820756e9SSandrine Bailleux * Disable intra-cluster coherency 17820756e9SSandrine Bailleux * --------------------------------------------- 18820756e9SSandrine Bailleux */ 19820756e9SSandrine Bailleuxfunc cortex_a35_disable_smp 205c7d12cbSSona Mathew sysreg_bit_clear CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT 21820756e9SSandrine Bailleux isb 22820756e9SSandrine Bailleux dsb sy 23820756e9SSandrine Bailleux ret 24820756e9SSandrine Bailleuxendfunc cortex_a35_disable_smp 25820756e9SSandrine Bailleux 2640eef67eSSona Mathewworkaround_reset_start cortex_a35, ERRATUM(855472), ERRATA_A35_855472 275c7d12cbSSona Mathew sysreg_bit_set CORTEX_A35_CPUACTLR_EL1, CORTEX_A35_CPUACTLR_EL1_ENDCCASCI 2840eef67eSSona Mathewworkaround_reset_end cortex_a35, ERRATUM(855472) 29cba71b70SLouis Mayencourt 3040eef67eSSona Mathewcheck_erratum_ls cortex_a35, ERRATUM(855472), CPU_REV(0, 0) 31cba71b70SLouis Mayencourt 32820756e9SSandrine Bailleux /* ------------------------------------------------- 33820756e9SSandrine Bailleux * The CPU Ops reset function for Cortex-A35. 34820756e9SSandrine Bailleux * ------------------------------------------------- 35820756e9SSandrine Bailleux */ 3640eef67eSSona Mathewcpu_reset_func_start cortex_a35 37820756e9SSandrine Bailleux /* --------------------------------------------- 38c66fad93SSandrine Bailleux * Enable the SMP bit. 39820756e9SSandrine Bailleux * --------------------------------------------- 40820756e9SSandrine Bailleux */ 415c7d12cbSSona Mathew sysreg_bit_set CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT 4240eef67eSSona Mathewcpu_reset_func_end cortex_a35 43820756e9SSandrine Bailleux 44820756e9SSandrine Bailleuxfunc cortex_a35_core_pwr_dwn 45820756e9SSandrine Bailleux mov x18, x30 46820756e9SSandrine Bailleux 47820756e9SSandrine Bailleux /* --------------------------------------------- 48820756e9SSandrine Bailleux * Flush L1 caches. 49820756e9SSandrine Bailleux * --------------------------------------------- 50820756e9SSandrine Bailleux */ 51820756e9SSandrine Bailleux mov x0, #DCCISW 52820756e9SSandrine Bailleux bl dcsw_op_level1 53820756e9SSandrine Bailleux 54820756e9SSandrine Bailleux /* --------------------------------------------- 55820756e9SSandrine Bailleux * Come out of intra cluster coherency 56820756e9SSandrine Bailleux * --------------------------------------------- 57820756e9SSandrine Bailleux */ 58820756e9SSandrine Bailleux mov x30, x18 59820756e9SSandrine Bailleux b cortex_a35_disable_smp 60820756e9SSandrine Bailleuxendfunc cortex_a35_core_pwr_dwn 61820756e9SSandrine Bailleux 62820756e9SSandrine Bailleuxfunc cortex_a35_cluster_pwr_dwn 63820756e9SSandrine Bailleux mov x18, x30 64820756e9SSandrine Bailleux 65820756e9SSandrine Bailleux /* --------------------------------------------- 66820756e9SSandrine Bailleux * Flush L1 caches. 67820756e9SSandrine Bailleux * --------------------------------------------- 68820756e9SSandrine Bailleux */ 69820756e9SSandrine Bailleux mov x0, #DCCISW 70820756e9SSandrine Bailleux bl dcsw_op_level1 71820756e9SSandrine Bailleux 72820756e9SSandrine Bailleux /* --------------------------------------------- 73820756e9SSandrine Bailleux * Disable the optional ACP. 74820756e9SSandrine Bailleux * --------------------------------------------- 75820756e9SSandrine Bailleux */ 76820756e9SSandrine Bailleux bl plat_disable_acp 77820756e9SSandrine Bailleux 78820756e9SSandrine Bailleux /* --------------------------------------------- 79820756e9SSandrine Bailleux * Flush L2 caches. 80820756e9SSandrine Bailleux * --------------------------------------------- 81820756e9SSandrine Bailleux */ 82820756e9SSandrine Bailleux mov x0, #DCCISW 83820756e9SSandrine Bailleux bl dcsw_op_level2 84820756e9SSandrine Bailleux 85820756e9SSandrine Bailleux /* --------------------------------------------- 86820756e9SSandrine Bailleux * Come out of intra cluster coherency 87820756e9SSandrine Bailleux * --------------------------------------------- 88820756e9SSandrine Bailleux */ 89820756e9SSandrine Bailleux mov x30, x18 90820756e9SSandrine Bailleux b cortex_a35_disable_smp 91820756e9SSandrine Bailleuxendfunc cortex_a35_cluster_pwr_dwn 92820756e9SSandrine Bailleux 93820756e9SSandrine Bailleux /* --------------------------------------------- 94820756e9SSandrine Bailleux * This function provides cortex_a35 specific 95820756e9SSandrine Bailleux * register information for crash reporting. 96820756e9SSandrine Bailleux * It needs to return with x6 pointing to 97820756e9SSandrine Bailleux * a list of register names in ascii and 98820756e9SSandrine Bailleux * x8 - x15 having values of registers to be 99820756e9SSandrine Bailleux * reported. 100820756e9SSandrine Bailleux * --------------------------------------------- 101820756e9SSandrine Bailleux */ 102820756e9SSandrine Bailleux.section .rodata.cortex_a35_regs, "aS" 103820756e9SSandrine Bailleuxcortex_a35_regs: /* The ascii list of register names to be reported */ 104820756e9SSandrine Bailleux .asciz "cpuectlr_el1", "" 105820756e9SSandrine Bailleux 106820756e9SSandrine Bailleuxfunc cortex_a35_cpu_reg_dump 107820756e9SSandrine Bailleux adr x6, cortex_a35_regs 108820756e9SSandrine Bailleux mrs x8, CORTEX_A35_CPUECTLR_EL1 109820756e9SSandrine Bailleux ret 110820756e9SSandrine Bailleuxendfunc cortex_a35_cpu_reg_dump 111820756e9SSandrine Bailleux 1125dd9dbb5SJeenu Viswambharandeclare_cpu_ops cortex_a35, CORTEX_A35_MIDR, \ 1135dd9dbb5SJeenu Viswambharan cortex_a35_reset_func, \ 1145dd9dbb5SJeenu Viswambharan cortex_a35_core_pwr_dwn, \ 1155dd9dbb5SJeenu Viswambharan cortex_a35_cluster_pwr_dwn 116