1/* 2 * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <cortex_a73.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13cpu_reset_prologue cortex_a73 14 15 /* --------------------------------------------- 16 * Disable intra-cluster coherency 17 * --------------------------------------------- 18 */ 19func cortex_a73_disable_smp 20 sysreg_bit_clear CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT 21 isb 22 dsb sy 23 ret 24endfunc cortex_a73_disable_smp 25 26/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */ 27add_erratum_entry cortex_a73, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960 28 29check_erratum_chosen cortex_a73, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960 30 31workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427 32 sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12) 33workaround_reset_end cortex_a73, ERRATUM(852427) 34 35check_erratum_ls cortex_a73, ERRATUM(852427), CPU_REV(0, 0) 36 37workaround_reset_start cortex_a73, ERRATUM(855423), ERRATA_A73_855423 38 sysreg_bit_set CORTEX_A73_IMP_DEF_REG2, BIT(7) 39workaround_reset_end cortex_a73, ERRATUM(855423) 40 41check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1) 42 43workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 44#if IMAGE_BL31 45 override_vector_table wa_cve_2017_5715_bpiall_vbar 46#endif /* IMAGE_BL31 */ 47workaround_reset_end cortex_a73, CVE(2017, 5715) 48 49check_erratum_custom_start cortex_a73, CVE(2017, 5715) 50 cpu_check_csv2 x0, 1f 51#if WORKAROUND_CVE_2017_5715 52 mov x0, #ERRATA_APPLIES 53#else 54 mov x0, #ERRATA_MISSING 55#endif 56 ret 571: 58 mov x0, #ERRATA_NOT_APPLIES 59 ret 60check_erratum_custom_end cortex_a73, CVE(2017, 5715) 61 62workaround_reset_start cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 63 sysreg_bit_set CORTEX_A73_IMP_DEF_REG1, CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE 64workaround_reset_end cortex_a73, CVE(2018, 3639) 65 66check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 67 68workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 69#if IMAGE_BL31 70 /* Skip installing vector table again for CVE_2022_23960 */ 71 adr x0, wa_cve_2017_5715_bpiall_vbar 72 mrs x1, vbar_el3 73 74 cmp x0, x1 75 b.eq 1f 76 msr vbar_el3, x0 771: 78#endif /* IMAGE_BL31 */ 79workaround_reset_end cortex_a73, CVE(2022, 23960) 80 81check_erratum_custom_start cortex_a73, CVE(2022, 23960) 82#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 83 cpu_check_csv2 x0, 1f 84 mov x0, #ERRATA_APPLIES 85 ret 86 1: 87#if WORKAROUND_CVE_2022_23960 88 mov x0, #ERRATA_APPLIES 89#else 90 mov x0, #ERRATA_MISSING 91#endif /* WORKAROUND_CVE_2022_23960 */ 92 ret 93#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 94 mov x0, #ERRATA_MISSING 95 ret 96check_erratum_custom_end cortex_a73, CVE(2022, 23960) 97 98 /* ------------------------------------------------- 99 * The CPU Ops reset function for Cortex-A73. 100 * ------------------------------------------------- 101 */ 102 103cpu_reset_func_start cortex_a73 104 /* --------------------------------------------- 105 * Enable the SMP bit. 106 * Clobbers : x0 107 * --------------------------------------------- 108 */ 109 sysreg_bit_set CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT 110cpu_reset_func_end cortex_a73 111 112func cortex_a73_core_pwr_dwn 113 mov x18, x30 114 115 /* --------------------------------------------- 116 * Flush L1 caches. 117 * --------------------------------------------- 118 */ 119 mov x0, #DCCISW 120 bl dcsw_op_level1 121 122 /* --------------------------------------------- 123 * Come out of intra cluster coherency 124 * --------------------------------------------- 125 */ 126 mov x30, x18 127 b cortex_a73_disable_smp 128endfunc cortex_a73_core_pwr_dwn 129 130func cortex_a73_cluster_pwr_dwn 131 mov x18, x30 132 133 /* --------------------------------------------- 134 * Flush L1 caches. 135 * --------------------------------------------- 136 */ 137 mov x0, #DCCISW 138 bl dcsw_op_level1 139 140 /* --------------------------------------------- 141 * Disable the optional ACP. 142 * --------------------------------------------- 143 */ 144 bl plat_disable_acp 145 146 /* --------------------------------------------- 147 * Flush L2 caches. 148 * --------------------------------------------- 149 */ 150 mov x0, #DCCISW 151 bl dcsw_op_level2 152 153 /* --------------------------------------------- 154 * Come out of intra cluster coherency 155 * --------------------------------------------- 156 */ 157 mov x30, x18 158 b cortex_a73_disable_smp 159endfunc cortex_a73_cluster_pwr_dwn 160 161 /* --------------------------------------------- 162 * This function provides cortex_a73 specific 163 * register information for crash reporting. 164 * It needs to return with x6 pointing to 165 * a list of register names in ascii and 166 * x8 - x15 having values of registers to be 167 * reported. 168 * --------------------------------------------- 169 */ 170.section .rodata.cortex_a73_regs, "aS" 171cortex_a73_regs: /* The ascii list of register names to be reported */ 172 .asciz "cpuectlr_el1", "l2merrsr_el1", "" 173 174func cortex_a73_cpu_reg_dump 175 adr x6, cortex_a73_regs 176 mrs x8, CORTEX_A73_CPUECTLR_EL1 177 mrs x9, CORTEX_A73_L2MERRSR_EL1 178 ret 179endfunc cortex_a73_cpu_reg_dump 180 181declare_cpu_ops cortex_a73, CORTEX_A73_MIDR, \ 182 cortex_a73_reset_func, \ 183 cortex_a73_core_pwr_dwn, \ 184 cortex_a73_cluster_pwr_dwn 185