19b476841SSoby Mathew/* 20d020822SBoyan Karatotev * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 39b476841SSoby Mathew * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 59b476841SSoby Mathew */ 6add40351SSoby Mathew#include <aem_generic.h> 79b476841SSoby Mathew#include <arch.h> 89b476841SSoby Mathew#include <asm_macros.S> 99b476841SSoby Mathew#include <cpu_macros.S> 109b476841SSoby Mathew 11*89dba82dSBoyan Karatotevcpu_reset_prologue aem_generic 12*89dba82dSBoyan Karatotev 13add40351SSoby Mathewfunc aem_generic_core_pwr_dwn 14add40351SSoby Mathew /* --------------------------------------------- 15ef430ff4SAlexei Fedorov * AEM model supports L3 caches in which case L2 16ef430ff4SAlexei Fedorov * will be private per core caches and flush 17ef430ff4SAlexei Fedorov * from L1 to L2 is not sufficient. 18add40351SSoby Mathew * --------------------------------------------- 19add40351SSoby Mathew */ 20ef430ff4SAlexei Fedorov mrs x1, clidr_el1 219b476841SSoby Mathew 22ef430ff4SAlexei Fedorov /* --------------------------------------------- 23ef430ff4SAlexei Fedorov * Check if L3 cache is implemented. 24ef430ff4SAlexei Fedorov * --------------------------------------------- 25ef430ff4SAlexei Fedorov */ 26ef430ff4SAlexei Fedorov tst x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3) 27ef430ff4SAlexei Fedorov 28ef430ff4SAlexei Fedorov /* --------------------------------------------- 29ef430ff4SAlexei Fedorov * There is no L3 cache, flush L1 to L2 only. 30ef430ff4SAlexei Fedorov * --------------------------------------------- 31ef430ff4SAlexei Fedorov */ 32ef430ff4SAlexei Fedorov mov x0, #DCCISW 33ef430ff4SAlexei Fedorov b.eq dcsw_op_level1 34ef430ff4SAlexei Fedorov 35ef430ff4SAlexei Fedorov mov x18, x30 36ef430ff4SAlexei Fedorov 37ef430ff4SAlexei Fedorov /* --------------------------------------------- 38ef430ff4SAlexei Fedorov * Flush L1 cache to L2. 39ef430ff4SAlexei Fedorov * --------------------------------------------- 40ef430ff4SAlexei Fedorov */ 41ef430ff4SAlexei Fedorov bl dcsw_op_level1 42ef430ff4SAlexei Fedorov mov x30, x18 43ef430ff4SAlexei Fedorov 44ef430ff4SAlexei Fedorov /* --------------------------------------------- 45ef430ff4SAlexei Fedorov * Flush L2 cache to L3. 46ef430ff4SAlexei Fedorov * --------------------------------------------- 47ef430ff4SAlexei Fedorov */ 48ef430ff4SAlexei Fedorov mov x0, #DCCISW 49ef430ff4SAlexei Fedorov b dcsw_op_level2 50ef430ff4SAlexei Fedorovendfunc aem_generic_core_pwr_dwn 519b476841SSoby Mathew 52add40351SSoby Mathewfunc aem_generic_cluster_pwr_dwn 53add40351SSoby Mathew /* --------------------------------------------- 54ef430ff4SAlexei Fedorov * Flush all caches to PoC. 55add40351SSoby Mathew * --------------------------------------------- 56add40351SSoby Mathew */ 57add40351SSoby Mathew mov x0, #DCCISW 58add40351SSoby Mathew b dcsw_op_all 598b779620SKévin Petitendfunc aem_generic_cluster_pwr_dwn 60add40351SSoby Mathew 610d020822SBoyan Karatotevcpu_reset_func_start aem_generic 620d020822SBoyan Karatotevcpu_reset_func_end aem_generic 630d020822SBoyan Karatotev 64d3f70af6SSoby Mathew /* --------------------------------------------- 65d3f70af6SSoby Mathew * This function provides cpu specific 66d3f70af6SSoby Mathew * register information for crash reporting. 67d3f70af6SSoby Mathew * It needs to return with x6 pointing to 68d3f70af6SSoby Mathew * a list of register names in ascii and 69d3f70af6SSoby Mathew * x8 - x15 having values of registers to be 70d3f70af6SSoby Mathew * reported. 71d3f70af6SSoby Mathew * --------------------------------------------- 72d3f70af6SSoby Mathew */ 736fa11a5eSSoby Mathew.section .rodata.aem_generic_regs, "aS" 746fa11a5eSSoby Mathewaem_generic_regs: /* The ascii list of register names to be reported */ 756fa11a5eSSoby Mathew .asciz "" /* no registers to report */ 766fa11a5eSSoby Mathew 77d3f70af6SSoby Mathewfunc aem_generic_cpu_reg_dump 786fa11a5eSSoby Mathew adr x6, aem_generic_regs 79d3f70af6SSoby Mathew ret 808b779620SKévin Petitendfunc aem_generic_cpu_reg_dump 81d3f70af6SSoby Mathew 82add40351SSoby Mathew 83add40351SSoby Mathew/* cpu_ops for Base AEM FVP */ 840d020822SBoyan Karatotevdeclare_cpu_ops aem_generic, BASE_AEM_MIDR, aem_generic_reset_func, \ 855dd9dbb5SJeenu Viswambharan aem_generic_core_pwr_dwn, \ 865dd9dbb5SJeenu Viswambharan aem_generic_cluster_pwr_dwn 879b476841SSoby Mathew 88add40351SSoby Mathew/* cpu_ops for Foundation FVP */ 890d020822SBoyan Karatotevdeclare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, aem_generic_reset_func, \ 905dd9dbb5SJeenu Viswambharan aem_generic_core_pwr_dwn, \ 915dd9dbb5SJeenu Viswambharan aem_generic_cluster_pwr_dwn 92