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Searched refs:CNTCR_OFF (Results 1 – 17 of 17) sorted by relevance

/rk3399_ARM-atf/drivers/renesas/common/timer/
H A Dtimer.c33 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + CNTCR_OFF), 0U); in rcar_pwrc_restore_timer_state()
48 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + CNTCR_OFF), in rcar_pwrc_restore_timer_state()
/rk3399_ARM-atf/drivers/nxp/timer/
H A Dnxp_timer.c107 mmio_write_32(g_nxp_timer_addr + CNTCR_OFF, in delay_timer_init()
140 mmio_write_32(g_nxp_timer_addr + CNTCR_OFF, in enable_init_timer()
/rk3399_ARM-atf/plat/renesas/rcar_gen4/
H A Dbl31_plat_setup.c77 mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); in bl31_platform_setup()
/rk3399_ARM-atf/plat/socionext/uniphier/
H A Duniphier_bl31_setup.c81 mmio_write_32(cntctl_base + CNTCR_OFF, CNTCR_FCREQ(0U) | CNTCR_EN); in bl31_platform_setup()
/rk3399_ARM-atf/drivers/st/clk/
H A Dstm32mp_clkfunc.c365 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); in stm32mp_stgen_config()
372 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); in stm32mp_stgen_config()
/rk3399_ARM-atf/plat/renesas/common/
H A Dbl31_plat_setup.c114 mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN); in bl31_platform_setup()
/rk3399_ARM-atf/plat/renesas/rcar_gen5/
H A Dbl31_plat_setup.c165 mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); in bl31_platform_setup()
/rk3399_ARM-atf/plat/imx/imx7/common/
H A Dimx7_bl2_el3_common.c130 mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, in imx7_setup_system_counter()
/rk3399_ARM-atf/plat/socionext/synquacer/
H A Dsq_bl31_setup.c200 mmio_write_32(SQ_SYS_CNTCTL_BASE + CNTCR_OFF, in bl31_platform_setup()
/rk3399_ARM-atf/plat/nuvoton/npcm845x/
H A Dnpcm845x_bl31_setup.c288 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, in bl31_platform_setup()
/rk3399_ARM-atf/plat/arm/common/sp_min/
H A Darm_sp_min_setup.c261 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, in sp_min_platform_setup()
/rk3399_ARM-atf/plat/arm/common/
H A Darm_bl31_setup.c446 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, in arm_bl31_platform_setup()
/rk3399_ARM-atf/plat/arm/board/fvp/
H A Dfvp_common.c545 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, in fvp_timer_init()
/rk3399_ARM-atf/plat/renesas/rzg/
H A Dbl2_plat_setup.c1018 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, in bl2_init_generic_timer()
/rk3399_ARM-atf/include/arch/aarch32/
H A Darch.h85 #define CNTCR_OFF U(0x000) macro
/rk3399_ARM-atf/plat/renesas/rcar/
H A Dbl2_plat_setup.c1416 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, in bl2_init_generic_timer()
/rk3399_ARM-atf/include/arch/aarch64/
H A Darch.h162 #define CNTCR_OFF U(0x000) macro