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Searched refs:CMD_0 (Results 1 – 13 of 13) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_pmic_wrap.h20 CMD_0 = 0U, /* 0x0 */ enumerator
H A Dmt_spm_pmic_wrap.c53 ._[CMD_0] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(80000), },
73 ._[CMD_0] = { BUCK_VCORE_ELR0_57, VOLT_TO_PMIC_VAL_57(80000), },
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_plat_spm_setting.h23 CMD_0, enumerator
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_pmic_wrap.h21 CMD_0 = 0, /* PMIC_WRAP_PHASE_ALLINONE */ enumerator
H A Dmt_spm_pmic_wrap.c61 ._[CMD_0] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(75000)),},
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_pmic_wrap.h20 CMD_0, /* 0x0 */ enumerator
H A Dmt_spm_pmic_wrap.c56 ._[CMD_0] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(72500),},
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_pmic_wrap.h20 CMD_0, /* 0x0 */ enumerator
H A Dmt_spm_pmic_wrap.c56 ._[CMD_0] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(75000),},
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_plat_spm_setting.h22 CMD_0, enumerator
H A Dmt_vcore_dvfsrc_plat.c222 spm_vcorefs_pwarp_cmd(CMD_0, VCORE_UV_TO_PMIC(v_opp_uv[5])); in spm_vcorefs_vcore_setting()
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/
H A Dspm_pmic_wrap.h21 CMD_0, /* 0x0 *//* PMIC_WRAP_PHASE_ALLINONE */ enumerator
H A Dspm_pmic_wrap.c59 ._[CMD_0] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(70000),},