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/OK3568_Linux_fs/kernel/sound/soc/ux500/
H A Dux500_msp_i2s.c141 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
169 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
206 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; in configure_protocol()
208 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
209 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; in configure_protocol()
211 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
225 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
226 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
258 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
264 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_gpuprops_backend.c36 struct kbase_gpuprops_regdump registers = { 0 }; in kbase_backend_gpuprops_get() local
39 registers.gpu_id = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID)); in kbase_backend_gpuprops_get()
41 registers.l2_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
44 registers.tiler_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
46 registers.mem_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
48 registers.mmu_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
50 registers.as_present = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
53 registers.js_present = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
56 registers.js_present = 0; in kbase_backend_gpuprops_get()
61 registers.js_features[i] = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/usb/cpia2/
H A Dcpia2_core.c247 cmd.buffer.registers[0].index = CPIA2_VC_ST_CTRL; in cpia2_do_command()
248 cmd.buffer.registers[0].value = CPIA2_VC_ST_CTRL_SRC_VC | in cpia2_do_command()
250 cmd.buffer.registers[1].index = CPIA2_VC_ST_CTRL; in cpia2_do_command()
251 cmd.buffer.registers[1].value = CPIA2_VC_ST_CTRL_SRC_VC | in cpia2_do_command()
260 cmd.buffer.registers[0].index = in cpia2_do_command()
262 cmd.buffer.registers[1].index = in cpia2_do_command()
264 cmd.buffer.registers[0].value = CPIA2_SYSTEM_CONTROL_CLEAR_ERR; in cpia2_do_command()
265 cmd.buffer.registers[1].value = in cpia2_do_command()
380 cmd.buffer.registers[0].index = CPIA2_VC_VC_TARGET_KB; in cpia2_do_command()
381 cmd.buffer.registers[0].value = param; in cpia2_do_command()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/radio/si470x/
H A Dradio-si470x-common.c185 radio->registers[SYSCONFIG2] &= ~SYSCONFIG2_BAND; in si470x_set_band()
186 radio->registers[SYSCONFIG2] |= radio->band << 6; in si470x_set_band()
203 if ((radio->registers[POWERCFG] & (POWERCFG_ENABLE|POWERCFG_DMUTE)) in si470x_set_chan()
209 radio->registers[CHANNEL] &= ~CHANNEL_CHAN; in si470x_set_chan()
210 radio->registers[CHANNEL] |= CHANNEL_TUNE | chan; in si470x_set_chan()
222 if ((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0) in si470x_set_chan()
229 radio->registers[CHANNEL] &= ~CHANNEL_TUNE; in si470x_set_chan()
242 switch ((radio->registers[SYSCONFIG2] & SYSCONFIG2_SPACE) >> 4) { in si470x_get_step()
265 chan = radio->registers[READCHAN] & READCHAN_READCHAN; in si470x_get_freq()
327 radio->registers[POWERCFG] |= POWERCFG_SEEK; in si470x_set_seek()
[all …]
H A Dradio-si470x-i2c.c99 radio->registers[regnr] = __be16_to_cpu(buf[READ_INDEX(regnr)]); in si470x_get_register()
121 buf[i] = __cpu_to_be16(radio->registers[WRITE_INDEX(i)]); in si470x_set_register()
155 radio->registers[i] = __be16_to_cpu(buf[READ_INDEX(i)]); in si470x_get_all_registers()
184 radio->registers[SYSCONFIG1] |= SYSCONFIG1_RDSIEN; in si470x_fops_open()
185 radio->registers[SYSCONFIG1] |= SYSCONFIG1_STCIEN; in si470x_fops_open()
186 radio->registers[SYSCONFIG1] &= ~SYSCONFIG1_GPIO2; in si470x_fops_open()
187 radio->registers[SYSCONFIG1] |= 0x1 << 2; in si470x_fops_open()
253 if (radio->registers[STATUSRSSI] & STATUSRSSI_STC) in si470x_i2c_interrupt()
257 if ((radio->registers[SYSCONFIG1] & SYSCONFIG1_RDS) == 0) in si470x_i2c_interrupt()
268 if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSR) == 0) in si470x_i2c_interrupt()
[all …]
H A Dradio-si470x-usb.c253 radio->registers[regnr] = get_unaligned_be16(&radio->usb_buf[1]); in si470x_get_register()
267 put_unaligned_be16(radio->registers[regnr], &radio->usb_buf[1]); in si470x_set_register()
294 radio->registers[regnr] = get_unaligned_be16( in si470x_get_all_registers()
388 radio->registers[STATUSRSSI] = in si470x_int_in_callback()
391 if (radio->registers[STATUSRSSI] & STATUSRSSI_STC) in si470x_int_in_callback()
394 if ((radio->registers[SYSCONFIG1] & SYSCONFIG1_RDS)) { in si470x_int_in_callback()
397 radio->registers[STATUSRSSI + regnr] = in si470x_int_in_callback()
401 if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSR) == 0) { in si470x_int_in_callback()
405 if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSS) == 0) { in si470x_int_in_callback()
412 bler = (radio->registers[STATUSRSSI] & in si470x_int_in_callback()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/lib/
H A Dstacktrace.c72 uint32_t registers[16]; member
226 ulong vsp = state->registers[SP]; in unwind_exec_insn()
234 state->registers[SP] += ((insn & INSN_VSP_SIZE_MASK) << 2) + 4; in unwind_exec_insn()
237 state->registers[SP] -= ((insn & INSN_VSP_SIZE_MASK) << 2) + 4; in unwind_exec_insn()
258 if (!pop_vsp(&state->registers[reg], &vsp, in unwind_exec_insn()
273 state->registers[SP] = in unwind_exec_insn()
274 state->registers[insn & INSN_STD_DATA_MASK]; in unwind_exec_insn()
287 if (!pop_vsp(&state->registers[reg], &vsp, in unwind_exec_insn()
295 if (!pop_vsp(&state->registers[14], &vsp, kernel_stack, in unwind_exec_insn()
319 if (!pop_vsp(&state->registers[reg], &vsp, in unwind_exec_insn()
[all …]
H A Dvectors_m.S14 mov r0, sp @ pass auto-saved registers as argument
19 mov r0, sp @ pass auto-saved registers as argument
24 mov r0, sp @ pass auto-saved registers as argument
29 mov r0, sp @ pass auto-saved registers as argument
34 mov r0, sp @ pass auto-saved registers as argument
/OK3568_Linux_fs/kernel/drivers/scsi/smartpqi/
H A Dsmartpqi_sis.c90 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_wait_for_ctrl_ready_with_timeout()
96 &ctrl_info->registers->sis_mailbox[7])); in sis_wait_for_ctrl_ready_with_timeout()
131 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_is_firmware_running()
141 readl(&ctrl_info->registers->sis_mailbox[7])); in sis_is_firmware_running()
148 return readl(&ctrl_info->registers->sis_firmware_status) & in sis_is_kernel_up()
160 struct pqi_ctrl_registers __iomem *registers; in sis_send_sync_cmd() local
166 registers = ctrl_info->registers; in sis_send_sync_cmd()
169 writel(cmd, &registers->sis_mailbox[0]); in sis_send_sync_cmd()
176 writel(params->mailbox[i], &registers->sis_mailbox[i]); in sis_send_sync_cmd()
180 &registers->sis_ctrl_to_host_doorbell_clear); in sis_send_sync_cmd()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/i2c/
H A Dmellanox,i2c-mlxbf.txt7 - reg : address offset and length of the device registers. The
8 registers consist of the following set of resources:
9 1) Smbus block registers.
10 2) Cause master registers.
11 3) Cause slave registers.
12 4) Cause coalesce registers (if compatible isn't set
19 - clock-frequency : bus frequency used to configure timing registers;
/OK3568_Linux_fs/kernel/drivers/char/agp/
H A Damd-k7-agp.c32 volatile u8 __iomem *registers; member
216 if (!amd_irongate_private.registers) { in amd_irongate_configure()
219 amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096); in amd_irongate_configure()
220 if (!amd_irongate_private.registers) in amd_irongate_configure()
225 writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE); in amd_irongate_configure()
226 readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */ in amd_irongate_configure()
235 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
237 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
238 readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */ in amd_irongate_configure()
246 writel(1, amd_irongate_private.registers+AMD_TLBFLUSH); in amd_irongate_configure()
[all …]
H A Dsworks-agp.c39 volatile u8 __iomem *registers; member
240 writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH); in serverworks_tlbflush()
242 while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) { in serverworks_tlbflush()
251 writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH); in serverworks_tlbflush()
253 while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) { in serverworks_tlbflush()
275 serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096); in serverworks_configure()
276 if (!serverworks_private.registers) { in serverworks_configure()
281 writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE); in serverworks_configure()
282 readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */ in serverworks_configure()
284 writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE); in serverworks_configure()
[all …]
H A Dintel-gtt.c66 u8 __iomem *registers; member
186 intel_private.registers = ioremap(reg_addr, KB(64)); in i810_setup()
187 if (!intel_private.registers) in i810_setup()
191 intel_private.registers+I810_PGETBL_CTL); in i810_setup()
195 if ((readl(intel_private.registers+I810_DRAM_CTL) in i810_setup()
207 writel(0, intel_private.registers+I810_PGETBL_CTL); in i810_cleanup()
365 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); in intel_gtt_stolen_size()
438 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); in i965_adjust_pgetbl_size()
440 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); in i965_adjust_pgetbl_size()
443 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); in i965_adjust_pgetbl_size()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.c22 struct a6xx_gpu_state_obj *registers; member
464 int count = RANGE(dbgahb->registers, j); in a6xx_get_dbgahb_cluster()
466 dbgahb->registers[j] - (dbgahb->base >> 2); in a6xx_get_dbgahb_cluster()
536 int count = RANGE(cluster->registers, j); in a6xx_get_cluster()
538 in += CRASHDUMP_READ(in, cluster->registers[j], in a6xx_get_cluster()
648 u32 count = RANGE(regs->registers, i); in a6xx_get_crashdumper_hlsq_registers()
650 regs->registers[i] - (regs->val0 >> 2); in a6xx_get_crashdumper_hlsq_registers()
688 u32 count = RANGE(regs->registers, i); in a6xx_get_crashdumper_registers()
690 in += CRASHDUMP_READ(in, regs->registers[i], count, out); in a6xx_get_crashdumper_registers()
718 regcount += RANGE(regs->registers, i); in a6xx_get_ahb_gpu_registers()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mips/
H A Dmscc.txt14 The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
20 - reg : Should contain registers location and length
31 The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
32 the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
37 - reg : Should contain registers location and length
47 The SoC has a few registers (HSIO) handling miscellaneous functionalities:
53 - reg : Should contain registers location and length
/OK3568_Linux_fs/kernel/drivers/gpio/
H A Dgpio-74x164.c24 u32 registers; member
38 chip->registers); in __gen_74x164_write_config()
44 u8 bank = chip->registers - 1 - offset / 8; in gen_74x164_get_value()
59 u8 bank = chip->registers - 1 - offset / 8; in gen_74x164_set_value()
82 for_each_set_clump8(offset, bankmask, mask, chip->registers * 8) { in gen_74x164_set_multiple()
83 bank = chip->registers - 1 - offset / 8; in gen_74x164_set_multiple()
141 chip->registers = nregs; in gen_74x164_probe()
142 chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers; in gen_74x164_probe()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/powerpc/nintendo/
H A Dwii.txt31 - reg : should contain the VI registers location and length
42 - reg : should contain the PI registers location and length
64 - reg : should contain the DSP registers location and length
76 - reg : should contain the SI registers location and length
87 - reg : should contain the AI registers location and length
97 - reg : should contain the EXI registers location and length
107 - reg : should contain the OHCI registers location and length
117 - reg : should contain the EHCI registers location and length
127 - reg : should contain the SDHCI registers location and length
136 - reg : should contain the IPC registers location and length
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dbrcm,amac.txt9 contains the information of registers in the same order as
11 - reg-names: Names of the registers.
12 "amac_base": Address and length of the GMAC registers
13 "idm_base": Address and length of the GMAC IDM registers
16 registers (required for Northstar2)
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dmvebu-pci.txt15 - ranges: ranges describing the MMIO registers to control the PCIe
21 The ranges describing the MMIO registers have the following layout:
28 registers of this PCIe interface, from the base of the internal
29 registers.
32 registers area. This range entry translates the '0x82000000 0 r' PCI
62 - assigned-addresses: reference to the MMIO registers used to control
97 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
98 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
99 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
100 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Ddesignware-pcie.txt37 automatic checking of CDM (Configuration Dependent Module) registers
38 for data corruption. CDM registers include standard PCIe configuration
39 space registers, Port Logic registers, DMA and iATU (internal Address
40 Translation Unit) registers.
55 reg = <0xdfc00000 0x0001000>, /* IP registers */
70 reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
71 <0xdfc01000 0x0001000>, /* IP registers 2 */
/OK3568_Linux_fs/kernel/Documentation/sh/
H A Dregister-banks.rst17 In the case of this type of banking, banked registers are mapped directly to
19 can still be used to reference the banked registers (as r0_bank ... r7_bank)
21 in mind when writing code that utilizes these banked registers, for obvious
23 be used rather effectively as scratch registers by the kernel.
25 Presently the kernel uses several of these registers.
28 registers when doing exception handling).
/OK3568_Linux_fs/kernel/drivers/net/dsa/mv88e6xxx/
H A Ddevlink.c272 u16 *registers; in mv88e6xxx_region_global_snapshot() local
275 registers = kmalloc_array(32, sizeof(u16), GFP_KERNEL); in mv88e6xxx_region_global_snapshot()
276 if (!registers) in mv88e6xxx_region_global_snapshot()
283 err = mv88e6xxx_g1_read(chip, i, &registers[i]); in mv88e6xxx_region_global_snapshot()
286 err = mv88e6xxx_g2_read(chip, i, &registers[i]); in mv88e6xxx_region_global_snapshot()
293 kfree(registers); in mv88e6xxx_region_global_snapshot()
297 *data = (u8 *)registers; in mv88e6xxx_region_global_snapshot()
428 u16 *registers; in mv88e6xxx_region_port_snapshot() local
431 registers = kmalloc_array(32, sizeof(u16), GFP_KERNEL); in mv88e6xxx_region_port_snapshot()
432 if (!registers) in mv88e6xxx_region_port_snapshot()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/marvell/
H A Dcoherency-fabric.txt18 - reg: Should contain coherency fabric registers location and
22 fabric registers, second pair for the per-CPU fabric registers.
25 for the per-CPU fabric registers.
28 for the per-CPU fabric registers.
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/edac/
H A Dsocfpga-eccmgr.txt18 - reg : Address and size for ECC error interrupt clear registers.
25 - reg : Address and size for ECC error interrupt clear registers.
60 containing the ECC manager registers.
74 - reg : Address and size for ECC error interrupt clear registers.
81 - reg : Address and size for ECC block registers.
88 - reg : Address and size for ECC block registers.
96 - reg : Address and size for ECC block registers.
104 - reg : Address and size for ECC block registers.
112 - reg : Address and size for ECC block registers.
120 - reg : Address and size for ECC block registers.
[all …]
/OK3568_Linux_fs/kernel/Documentation/driver-api/media/drivers/
H A Dcpia2_devel.rst35 The cameras appear externally as three sets of registers. Setting register
42 registers that control housekeeping functions such as powering up the video
43 processor. The video processor is the VP block. These registers control
44 how the video from the sensor is processed. Examples are timing registers,
49 of these registers and the possible values for most of them.
51 One or more registers can be set or read by sending a usb control message to
53 of contiguous registers. Random mode reads or writes random registers with

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