Searched refs:WRITE_DATA_DST_SEL (Results 1 – 15 of 15) sorted by relevance
152 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
110 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
89 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
142 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
260 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
897 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()5198 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5206 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5214 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5222 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()6303 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()6312 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()7155 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_ce_meta()7188 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_de_meta()
3281 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_wreg()4107 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4115 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4123 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4131 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
1010 WRITE_DATA_DST_SEL(0) | in gfx_v9_0_write_data_to_reg()1100 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()5437 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5446 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5470 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_ce_meta()5492 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_de_meta()
1700 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3420 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()3518 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v10_0_ring_test_ib()7926 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()7935 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8068 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_ce_meta()8102 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_de_meta()
2364 WRITE_DATA_DST_SEL(0))); in gfx_v6_0_ring_emit_wreg()
1637 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3752 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()5695 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5709 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5716 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5727 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5738 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
1728 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
5082 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5097 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5105 WRITE_DATA_DST_SEL(0))); in si_vm_flush()