Searched +full:vf610 +full:- +full:lpuart (Results 1 – 16 of 16) sorted by relevance
4 * SPDX-License-Identifier: GPL-2.0+ or X117 #include <dt-bindings/gpio/gpio.h>29 #address-cells = <1>;30 #size-cells = <1>;31 compatible = "simple-bus";34 aips0: aips-bus@40000000 {35 compatible = "fsl,aips-bus", "simple-bus";36 #address-cells = <1>;37 #size-cells = <1>;42 compatible = "fsl,vf610-lpuart";[all …]
2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.4 * Copyright (C) 2014-2015, Freescale Semiconductor17 interrupt-parent = <&gic>;20 compatible = "fixed-clock";21 #clock-cells = <0>;22 clock-frequency = <100000000>;23 clock-output-names = "sysclk";26 gic: interrupt-controller@1400000 {27 compatible = "arm,gic-400";28 #interrupt-cells = <3>;[all …]
4 * Copyright 2013-2015 Freescale Semiconductor, Inc.6 * SPDX-License-Identifier: GPL-2.0+10 #include <dt-bindings/interrupt-controller/arm-gic.h>14 interrupt-parent = <&gic>;27 #address-cells = <1>;28 #size-cells = <0>;31 compatible = "arm,cortex-a7";38 compatible = "arm,cortex-a7";46 compatible = "arm,armv7-timer";54 compatible = "arm,cortex-a7-pmu";[all …]
2 * Device Tree Include file for Freescale Layerscape-1046A family SoC.17 interrupt-parent = <&gic>;20 compatible = "fixed-clock";21 #clock-cells = <0>;22 clock-frequency = <100000000>;23 clock-output-names = "sysclk";26 gic: interrupt-controller@1400000 {27 compatible = "arm,gic-400";28 #interrupt-cells = <3>;29 interrupt-controller;[all …]
2 # SPDX-License-Identifier: GPL-2.0+5 dtb-$(CONFIG_AT91FAMILY) += at91sam9260-smartweb.dtb \6 at91sam9g20-taurus.dtb \7 at91sam9g45-corvus.dtb \8 at91sam9g45-gurnard.dtb10 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb11 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb12 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \13 exynos4210-smdkv310.dtb \14 exynos4210-universal_c210.dtb \[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Freescale low power universal asynchronous receiver/transmitter (lpuart)10 - Fugang Duan <fugang.duan@nxp.com>13 - $ref: "rs485.yaml"18 - enum:19 - fsl,vf610-lpuart20 - fsl,ls1021a-lpuart[all …]
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)5 #include "vf610-pinfunc.h"6 #include <dt-bindings/clock/vf610-clock.h>7 #include <dt-bindings/interrupt-controller/irq.h>8 #include <dt-bindings/gpio/gpio.h>32 compatible = "fixed-clock";33 #clock-cells = <0>;34 clock-frequency = <24000000>;38 compatible = "fixed-clock";39 #clock-cells = <0>;[all …]
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.4 * This file is dual-licensed: you can use it either under the terms22 * MA 02110-1301 USA48 #include <dt-bindings/interrupt-controller/arm-gic.h>49 #include <dt-bindings/thermal/thermal.h>52 #address-cells = <2>;53 #size-cells = <2>;55 interrupt-parent = <&gic>;73 #address-cells = <1>;74 #size-cells = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+4 * Copyright 2017-2018 NXP8 #include <dt-bindings/clock/imx7ulp-clock.h>9 #include <dt-bindings/gpio/gpio.h>10 #include <dt-bindings/interrupt-controller/arm-gic.h>12 #include "imx7ulp-pinfunc.h"15 interrupt-parent = <&intc>;17 #address-cells = <1>;18 #size-cells = <1>;37 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)3 * Device Tree Include file for NXP Layerscape-1028A family SoC.5 * Copyright 2018-2020 NXP11 #include <dt-bindings/interrupt-controller/arm-gic.h>12 #include <dt-bindings/thermal/thermal.h>16 interrupt-parent = <&gic>;17 #address-cells = <2>;18 #size-cells = <2>;25 #address-cells = <1>;26 #size-cells = <0>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)3 * Device Tree Include file for NXP Layerscape-1046A family SoC.11 #include <dt-bindings/interrupt-controller/arm-gic.h>12 #include <dt-bindings/thermal/thermal.h>16 interrupt-parent = <&gic>;17 #address-cells = <2>;18 #size-cells = <2>;35 #address-cells = <1>;36 #size-cells = <0>;40 compatible = "arm,cortex-a72";[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)3 * Device Tree Include file for NXP Layerscape-1043A family SoC.5 * Copyright 2014-2015 Freescale Semiconductor, Inc.11 #include <dt-bindings/thermal/thermal.h>12 #include <dt-bindings/interrupt-controller/arm-gic.h>16 interrupt-parent = <&gic>;17 #address-cells = <2>;18 #size-cells = <2>;34 #address-cells = <1>;35 #size-cells = <0>;[all …]
4 * SPDX-License-Identifier: GPL-2.0+14 #include <asm/arch/imx-regs.h>99 struct lpuart_serial_platdata *plat = dev->platdata; in is_lpuart32()101 return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG; in is_lpuart32()107 struct lpuart_fsl *base = plat->reg; in _lpuart_serial_setbrg()113 /* place adjustment later - n/32 BRFA */ in _lpuart_serial_setbrg()114 __raw_writeb(sbr >> 8, &base->ubdh); in _lpuart_serial_setbrg()115 __raw_writeb(sbr & 0xff, &base->ubdl); in _lpuart_serial_setbrg()120 struct lpuart_fsl *base = plat->reg; in _lpuart_serial_getc()121 while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR))) in _lpuart_serial_getc()[all …]
11 Select a default baudrate, where "default" has a driver-specific19 # non-dm serial code32 In very space-constrained devices even the full UART driver is too34 This option enables the full UART in U-Boot, so if is it disabled,42 In very space-constrained devices even the full UART driver is too105 The debug UART is intended for use very early in U-Boot to debug109 - Make sure your UART supports this interface110 - Enable CONFIG_DEBUG_UART111 - Enable the CONFIG for your UART to tell it to provide this interface113 - Define the required settings as needed (see below)[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Freescale lpuart serial port driver5 * Copyright 2012-2014 Freescale Semiconductor, Inc.10 #include <linux/dma-mapping.h>23 /* All registers are 8-bit width */112 /* 32-bit register definition */225 #define DRIVER_NAME "fsl-lpuart"229 /* IMX lpuart has four extra unused regs located at the beginning */302 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },303 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },[all …]
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