1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ or X11 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun/include/ "skeleton.dtsi" 7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun aliases { 11*4882a593Smuzhiyun gpio0 = &gpio0; 12*4882a593Smuzhiyun gpio1 = &gpio1; 13*4882a593Smuzhiyun gpio2 = &gpio2; 14*4882a593Smuzhiyun gpio3 = &gpio3; 15*4882a593Smuzhiyun gpio4 = &gpio4; 16*4882a593Smuzhiyun serial0 = &uart0; 17*4882a593Smuzhiyun serial1 = &uart1; 18*4882a593Smuzhiyun serial2 = &uart2; 19*4882a593Smuzhiyun serial3 = &uart3; 20*4882a593Smuzhiyun serial4 = &uart4; 21*4882a593Smuzhiyun serial5 = &uart5; 22*4882a593Smuzhiyun spi0 = &dspi0; 23*4882a593Smuzhiyun spi1 = &dspi1; 24*4882a593Smuzhiyun ehci0 = &ehci0; 25*4882a593Smuzhiyun ehci1 = &ehci1; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun soc { 29*4882a593Smuzhiyun #address-cells = <1>; 30*4882a593Smuzhiyun #size-cells = <1>; 31*4882a593Smuzhiyun compatible = "simple-bus"; 32*4882a593Smuzhiyun ranges; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun aips0: aips-bus@40000000 { 35*4882a593Smuzhiyun compatible = "fsl,aips-bus", "simple-bus"; 36*4882a593Smuzhiyun #address-cells = <1>; 37*4882a593Smuzhiyun #size-cells = <1>; 38*4882a593Smuzhiyun reg = <0x40000000 0x00070000>; 39*4882a593Smuzhiyun ranges; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun uart0: serial@40027000 { 42*4882a593Smuzhiyun compatible = "fsl,vf610-lpuart"; 43*4882a593Smuzhiyun reg = <0x40027000 0x1000>; 44*4882a593Smuzhiyun status = "disabled"; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun uart1: serial@40028000 { 48*4882a593Smuzhiyun compatible = "fsl,vf610-lpuart"; 49*4882a593Smuzhiyun reg = <0x40028000 0x1000>; 50*4882a593Smuzhiyun status = "disabled"; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun uart2: serial@40029000 { 54*4882a593Smuzhiyun compatible = "fsl,vf610-lpuart"; 55*4882a593Smuzhiyun reg = <0x40029000 0x1000>; 56*4882a593Smuzhiyun status = "disabled"; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun uart3: serial@4002a000 { 60*4882a593Smuzhiyun compatible = "fsl,vf610-lpuart"; 61*4882a593Smuzhiyun reg = <0x4002a000 0x1000>; 62*4882a593Smuzhiyun status = "disabled"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun dspi0: dspi0@4002c000 { 66*4882a593Smuzhiyun #address-cells = <1>; 67*4882a593Smuzhiyun #size-cells = <0>; 68*4882a593Smuzhiyun compatible = "fsl,vf610-dspi"; 69*4882a593Smuzhiyun reg = <0x4002c000 0x1000>; 70*4882a593Smuzhiyun num-cs = <5>; 71*4882a593Smuzhiyun status = "disabled"; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun dspi1: dspi1@4002d000 { 75*4882a593Smuzhiyun #address-cells = <1>; 76*4882a593Smuzhiyun #size-cells = <0>; 77*4882a593Smuzhiyun compatible = "fsl,vf610-dspi"; 78*4882a593Smuzhiyun reg = <0x4002d000 0x1000>; 79*4882a593Smuzhiyun num-cs = <5>; 80*4882a593Smuzhiyun status = "disabled"; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun qspi0: quadspi@40044000 { 84*4882a593Smuzhiyun #address-cells = <1>; 85*4882a593Smuzhiyun #size-cells = <0>; 86*4882a593Smuzhiyun compatible = "fsl,vf610-qspi"; 87*4882a593Smuzhiyun reg = <0x40044000 0x1000>, 88*4882a593Smuzhiyun <0x20000000 0x10000000>; 89*4882a593Smuzhiyun reg-names = "QuadSPI", "QuadSPI-memory"; 90*4882a593Smuzhiyun status = "disabled"; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun gpio0: gpio@40049000 { 94*4882a593Smuzhiyun compatible = "fsl,vf610-gpio"; 95*4882a593Smuzhiyun reg = <0x400ff000 0x40>; 96*4882a593Smuzhiyun #gpio-cells = <2>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun gpio1: gpio@4004a000 { 100*4882a593Smuzhiyun compatible = "fsl,vf610-gpio"; 101*4882a593Smuzhiyun reg = <0x400ff040 0x40>; 102*4882a593Smuzhiyun #gpio-cells = <2>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun gpio2: gpio@4004b000 { 106*4882a593Smuzhiyun compatible = "fsl,vf610-gpio"; 107*4882a593Smuzhiyun reg = <0x400ff080 0x40>; 108*4882a593Smuzhiyun #gpio-cells = <2>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun gpio3: gpio@4004c000 { 112*4882a593Smuzhiyun compatible = "fsl,vf610-gpio"; 113*4882a593Smuzhiyun reg = <0x400ff0c0 0x40>; 114*4882a593Smuzhiyun #gpio-cells = <2>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun gpio4: gpio@4004d000 { 118*4882a593Smuzhiyun compatible = "fsl,vf610-gpio"; 119*4882a593Smuzhiyun reg = <0x400ff100 0x40>; 120*4882a593Smuzhiyun #gpio-cells = <2>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun ehci0: ehci@40034000 { 124*4882a593Smuzhiyun compatible = "fsl,vf610-usb"; 125*4882a593Smuzhiyun reg = <0x40034000 0x800>; 126*4882a593Smuzhiyun status = "disabled"; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun aips1: aips-bus@40080000 { 131*4882a593Smuzhiyun compatible = "fsl,aips-bus", "simple-bus"; 132*4882a593Smuzhiyun #address-cells = <1>; 133*4882a593Smuzhiyun #size-cells = <1>; 134*4882a593Smuzhiyun reg = <0x40080000 0x0007f000>; 135*4882a593Smuzhiyun ranges; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun uart4: serial@400a9000 { 138*4882a593Smuzhiyun compatible = "fsl,vf610-lpuart"; 139*4882a593Smuzhiyun reg = <0x400a9000 0x1000>; 140*4882a593Smuzhiyun status = "disabled"; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun uart5: serial@400aa000 { 144*4882a593Smuzhiyun compatible = "fsl,vf610-lpuart"; 145*4882a593Smuzhiyun reg = <0x400aa000 0x1000>; 146*4882a593Smuzhiyun status = "disabled"; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun ehci1: ehci@400b4000 { 150*4882a593Smuzhiyun compatible = "fsl,vf610-usb"; 151*4882a593Smuzhiyun reg = <0x400b4000 0x800>; 152*4882a593Smuzhiyun status = "disabled"; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun}; 157