xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/vfxxx.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Copyright 2013 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun#include "vf610-pinfunc.h"
6*4882a593Smuzhiyun#include <dt-bindings/clock/vf610-clock.h>
7*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	aliases {
12*4882a593Smuzhiyun		can0 = &can0;
13*4882a593Smuzhiyun		can1 = &can1;
14*4882a593Smuzhiyun		ethernet0 = &fec0;
15*4882a593Smuzhiyun		ethernet1 = &fec1;
16*4882a593Smuzhiyun		serial0 = &uart0;
17*4882a593Smuzhiyun		serial1 = &uart1;
18*4882a593Smuzhiyun		serial2 = &uart2;
19*4882a593Smuzhiyun		serial3 = &uart3;
20*4882a593Smuzhiyun		serial4 = &uart4;
21*4882a593Smuzhiyun		serial5 = &uart5;
22*4882a593Smuzhiyun		gpio0 = &gpio0;
23*4882a593Smuzhiyun		gpio1 = &gpio1;
24*4882a593Smuzhiyun		gpio2 = &gpio2;
25*4882a593Smuzhiyun		gpio3 = &gpio3;
26*4882a593Smuzhiyun		gpio4 = &gpio4;
27*4882a593Smuzhiyun		usbphy0 = &usbphy0;
28*4882a593Smuzhiyun		usbphy1 = &usbphy1;
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	fxosc: fxosc {
32*4882a593Smuzhiyun		compatible = "fixed-clock";
33*4882a593Smuzhiyun		#clock-cells = <0>;
34*4882a593Smuzhiyun		clock-frequency = <24000000>;
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun	sxosc: sxosc {
38*4882a593Smuzhiyun		compatible = "fixed-clock";
39*4882a593Smuzhiyun		#clock-cells = <0>;
40*4882a593Smuzhiyun		clock-frequency = <32768>;
41*4882a593Smuzhiyun	};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun	reboot: syscon-reboot {
44*4882a593Smuzhiyun		compatible = "syscon-reboot";
45*4882a593Smuzhiyun		regmap = <&src>;
46*4882a593Smuzhiyun		offset = <0x0>;
47*4882a593Smuzhiyun		mask = <0x1000>;
48*4882a593Smuzhiyun	};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun	tempsensor: iio-hwmon {
51*4882a593Smuzhiyun		compatible = "iio-hwmon";
52*4882a593Smuzhiyun		io-channels = <&adc0 16>, <&adc1 16>;
53*4882a593Smuzhiyun	};
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun	soc {
56*4882a593Smuzhiyun		#address-cells = <1>;
57*4882a593Smuzhiyun		#size-cells = <1>;
58*4882a593Smuzhiyun		compatible = "simple-bus";
59*4882a593Smuzhiyun		interrupt-parent = <&mscm_ir>;
60*4882a593Smuzhiyun		ranges;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun		aips0: bus@40000000 {
63*4882a593Smuzhiyun			compatible = "fsl,aips-bus", "simple-bus";
64*4882a593Smuzhiyun			#address-cells = <1>;
65*4882a593Smuzhiyun			#size-cells = <1>;
66*4882a593Smuzhiyun			reg = <0x40000000 0x00070000>;
67*4882a593Smuzhiyun			ranges;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun			mscm_cpucfg: cpucfg@40001000 {
70*4882a593Smuzhiyun				compatible = "fsl,vf610-mscm-cpucfg", "syscon";
71*4882a593Smuzhiyun				reg = <0x40001000 0x800>;
72*4882a593Smuzhiyun			};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun			mscm_ir: interrupt-controller@40001800 {
75*4882a593Smuzhiyun				compatible = "fsl,vf610-mscm-ir";
76*4882a593Smuzhiyun				reg = <0x40001800 0x400>;
77*4882a593Smuzhiyun				fsl,cpucfg = <&mscm_cpucfg>;
78*4882a593Smuzhiyun				interrupt-controller;
79*4882a593Smuzhiyun				#interrupt-cells = <2>;
80*4882a593Smuzhiyun			};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun			edma0: dma-controller@40018000 {
83*4882a593Smuzhiyun				#dma-cells = <2>;
84*4882a593Smuzhiyun				compatible = "fsl,vf610-edma";
85*4882a593Smuzhiyun				reg = <0x40018000 0x2000>,
86*4882a593Smuzhiyun					<0x40024000 0x1000>,
87*4882a593Smuzhiyun					<0x40025000 0x1000>;
88*4882a593Smuzhiyun				dma-channels = <32>;
89*4882a593Smuzhiyun				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
90*4882a593Smuzhiyun						<9 IRQ_TYPE_LEVEL_HIGH>;
91*4882a593Smuzhiyun				interrupt-names = "edma-tx", "edma-err";
92*4882a593Smuzhiyun				clock-names = "dmamux0", "dmamux1";
93*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_DMAMUX0>,
94*4882a593Smuzhiyun					<&clks VF610_CLK_DMAMUX1>;
95*4882a593Smuzhiyun				status = "disabled";
96*4882a593Smuzhiyun			};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun			can0: flexcan@40020000 {
99*4882a593Smuzhiyun				compatible = "fsl,vf610-flexcan";
100*4882a593Smuzhiyun				reg = <0x40020000 0x4000>;
101*4882a593Smuzhiyun				interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
102*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_FLEXCAN0>,
103*4882a593Smuzhiyun					 <&clks VF610_CLK_FLEXCAN0>;
104*4882a593Smuzhiyun				clock-names = "ipg", "per";
105*4882a593Smuzhiyun				status = "disabled";
106*4882a593Smuzhiyun			};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun			uart0: serial@40027000 {
109*4882a593Smuzhiyun				compatible = "fsl,vf610-lpuart";
110*4882a593Smuzhiyun				reg = <0x40027000 0x1000>;
111*4882a593Smuzhiyun				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
112*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_UART0>;
113*4882a593Smuzhiyun				clock-names = "ipg";
114*4882a593Smuzhiyun				dmas = <&edma0 0 2>,
115*4882a593Smuzhiyun					<&edma0 0 3>;
116*4882a593Smuzhiyun				dma-names = "rx","tx";
117*4882a593Smuzhiyun				status = "disabled";
118*4882a593Smuzhiyun			};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun			uart1: serial@40028000 {
121*4882a593Smuzhiyun				compatible = "fsl,vf610-lpuart";
122*4882a593Smuzhiyun				reg = <0x40028000 0x1000>;
123*4882a593Smuzhiyun				interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
124*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_UART1>;
125*4882a593Smuzhiyun				clock-names = "ipg";
126*4882a593Smuzhiyun				dmas = <&edma0 0 4>,
127*4882a593Smuzhiyun					<&edma0 0 5>;
128*4882a593Smuzhiyun				dma-names = "rx","tx";
129*4882a593Smuzhiyun				status = "disabled";
130*4882a593Smuzhiyun			};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun			uart2: serial@40029000 {
133*4882a593Smuzhiyun				compatible = "fsl,vf610-lpuart";
134*4882a593Smuzhiyun				reg = <0x40029000 0x1000>;
135*4882a593Smuzhiyun				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
136*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_UART2>;
137*4882a593Smuzhiyun				clock-names = "ipg";
138*4882a593Smuzhiyun				dmas = <&edma0 0 6>,
139*4882a593Smuzhiyun					<&edma0 0 7>;
140*4882a593Smuzhiyun				dma-names = "rx","tx";
141*4882a593Smuzhiyun				status = "disabled";
142*4882a593Smuzhiyun			};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun			uart3: serial@4002a000 {
145*4882a593Smuzhiyun				compatible = "fsl,vf610-lpuart";
146*4882a593Smuzhiyun				reg = <0x4002a000 0x1000>;
147*4882a593Smuzhiyun				interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
148*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_UART3>;
149*4882a593Smuzhiyun				clock-names = "ipg";
150*4882a593Smuzhiyun				dmas = <&edma0 0 8>,
151*4882a593Smuzhiyun					<&edma0 0 9>;
152*4882a593Smuzhiyun				dma-names = "rx","tx";
153*4882a593Smuzhiyun				status = "disabled";
154*4882a593Smuzhiyun			};
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun			dspi0: spi@4002c000 {
157*4882a593Smuzhiyun				#address-cells = <1>;
158*4882a593Smuzhiyun				#size-cells = <0>;
159*4882a593Smuzhiyun				compatible = "fsl,vf610-dspi";
160*4882a593Smuzhiyun				reg = <0x4002c000 0x1000>;
161*4882a593Smuzhiyun				interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
162*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_DSPI0>;
163*4882a593Smuzhiyun				clock-names = "dspi";
164*4882a593Smuzhiyun				spi-num-chipselects = <6>;
165*4882a593Smuzhiyun				dmas = <&edma1 1 12>,
166*4882a593Smuzhiyun					<&edma1 1 13>;
167*4882a593Smuzhiyun				dma-names = "rx", "tx";
168*4882a593Smuzhiyun				status = "disabled";
169*4882a593Smuzhiyun			};
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun			dspi1: spi@4002d000 {
172*4882a593Smuzhiyun				#address-cells = <1>;
173*4882a593Smuzhiyun				#size-cells = <0>;
174*4882a593Smuzhiyun				compatible = "fsl,vf610-dspi";
175*4882a593Smuzhiyun				reg = <0x4002d000 0x1000>;
176*4882a593Smuzhiyun				interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
177*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_DSPI1>;
178*4882a593Smuzhiyun				clock-names = "dspi";
179*4882a593Smuzhiyun				spi-num-chipselects = <4>;
180*4882a593Smuzhiyun				dmas = <&edma1 1 14>,
181*4882a593Smuzhiyun					<&edma1 1 15>;
182*4882a593Smuzhiyun				dma-names = "rx", "tx";
183*4882a593Smuzhiyun				status = "disabled";
184*4882a593Smuzhiyun			};
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun			sai0: sai@4002f000 {
187*4882a593Smuzhiyun				compatible = "fsl,vf610-sai";
188*4882a593Smuzhiyun				reg = <0x4002f000 0x1000>;
189*4882a593Smuzhiyun				interrupts = <84 IRQ_TYPE_LEVEL_HIGH>;
190*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_SAI0>,
191*4882a593Smuzhiyun					<&clks VF610_CLK_SAI0_DIV>,
192*4882a593Smuzhiyun					<&clks 0>, <&clks 0>;
193*4882a593Smuzhiyun				clock-names = "bus", "mclk1", "mclk2", "mclk3";
194*4882a593Smuzhiyun				dma-names = "tx", "rx";
195*4882a593Smuzhiyun				dmas = <&edma0 0 17>,
196*4882a593Smuzhiyun					<&edma0 0 16>;
197*4882a593Smuzhiyun				status = "disabled";
198*4882a593Smuzhiyun			};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun			sai1: sai@40030000 {
201*4882a593Smuzhiyun				compatible = "fsl,vf610-sai";
202*4882a593Smuzhiyun				reg = <0x40030000 0x1000>;
203*4882a593Smuzhiyun				interrupts = <85 IRQ_TYPE_LEVEL_HIGH>;
204*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_SAI1>,
205*4882a593Smuzhiyun					<&clks VF610_CLK_SAI1_DIV>,
206*4882a593Smuzhiyun					<&clks 0>, <&clks 0>;
207*4882a593Smuzhiyun				clock-names = "bus", "mclk1", "mclk2", "mclk3";
208*4882a593Smuzhiyun				dma-names = "tx", "rx";
209*4882a593Smuzhiyun				dmas = <&edma0 0 19>,
210*4882a593Smuzhiyun					<&edma0 0 18>;
211*4882a593Smuzhiyun				status = "disabled";
212*4882a593Smuzhiyun			};
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun			sai2: sai@40031000 {
215*4882a593Smuzhiyun				compatible = "fsl,vf610-sai";
216*4882a593Smuzhiyun				reg = <0x40031000 0x1000>;
217*4882a593Smuzhiyun				interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
218*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_SAI2>,
219*4882a593Smuzhiyun					<&clks VF610_CLK_SAI2_DIV>,
220*4882a593Smuzhiyun					<&clks 0>, <&clks 0>;
221*4882a593Smuzhiyun				clock-names = "bus", "mclk1", "mclk2", "mclk3";
222*4882a593Smuzhiyun				dma-names = "tx", "rx";
223*4882a593Smuzhiyun				dmas = <&edma0 0 21>,
224*4882a593Smuzhiyun					<&edma0 0 20>;
225*4882a593Smuzhiyun				status = "disabled";
226*4882a593Smuzhiyun			};
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun			sai3: sai@40032000 {
229*4882a593Smuzhiyun				compatible = "fsl,vf610-sai";
230*4882a593Smuzhiyun				reg = <0x40032000 0x1000>;
231*4882a593Smuzhiyun				interrupts = <87 IRQ_TYPE_LEVEL_HIGH>;
232*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_SAI3>,
233*4882a593Smuzhiyun					<&clks VF610_CLK_SAI3_DIV>,
234*4882a593Smuzhiyun					<&clks 0>, <&clks 0>;
235*4882a593Smuzhiyun				clock-names = "bus", "mclk1", "mclk2", "mclk3";
236*4882a593Smuzhiyun				dma-names = "tx", "rx";
237*4882a593Smuzhiyun				dmas = <&edma0 1 9>,
238*4882a593Smuzhiyun					<&edma0 1 8>;
239*4882a593Smuzhiyun				status = "disabled";
240*4882a593Smuzhiyun			};
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun			pit: pit@40037000 {
243*4882a593Smuzhiyun				compatible = "fsl,vf610-pit";
244*4882a593Smuzhiyun				reg = <0x40037000 0x1000>;
245*4882a593Smuzhiyun				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
246*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_PIT>;
247*4882a593Smuzhiyun				clock-names = "pit";
248*4882a593Smuzhiyun			};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun			pwm0: pwm@40038000 {
251*4882a593Smuzhiyun				compatible = "fsl,vf610-ftm-pwm";
252*4882a593Smuzhiyun				#pwm-cells = <3>;
253*4882a593Smuzhiyun				reg = <0x40038000 0x1000>;
254*4882a593Smuzhiyun				clock-names = "ftm_sys", "ftm_ext",
255*4882a593Smuzhiyun					      "ftm_fix", "ftm_cnt_clk_en";
256*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_FTM0>,
257*4882a593Smuzhiyun					<&clks VF610_CLK_FTM0_EXT_SEL>,
258*4882a593Smuzhiyun					<&clks VF610_CLK_FTM0_FIX_SEL>,
259*4882a593Smuzhiyun					<&clks VF610_CLK_FTM0_EXT_FIX_EN>;
260*4882a593Smuzhiyun				status = "disabled";
261*4882a593Smuzhiyun			};
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun			pwm1: pwm@40039000 {
264*4882a593Smuzhiyun				compatible = "fsl,vf610-ftm-pwm";
265*4882a593Smuzhiyun				#pwm-cells = <3>;
266*4882a593Smuzhiyun				reg = <0x40039000 0x1000>;
267*4882a593Smuzhiyun				clock-names = "ftm_sys", "ftm_ext",
268*4882a593Smuzhiyun					      "ftm_fix", "ftm_cnt_clk_en";
269*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_FTM1>,
270*4882a593Smuzhiyun					<&clks VF610_CLK_FTM1_EXT_SEL>,
271*4882a593Smuzhiyun					<&clks VF610_CLK_FTM1_FIX_SEL>,
272*4882a593Smuzhiyun					<&clks VF610_CLK_FTM1_EXT_FIX_EN>;
273*4882a593Smuzhiyun				status = "disabled";
274*4882a593Smuzhiyun			};
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun			adc0: adc@4003b000 {
277*4882a593Smuzhiyun				compatible = "fsl,vf610-adc";
278*4882a593Smuzhiyun				reg = <0x4003b000 0x1000>;
279*4882a593Smuzhiyun				interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
280*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_ADC0>;
281*4882a593Smuzhiyun				clock-names = "adc";
282*4882a593Smuzhiyun				#io-channel-cells = <1>;
283*4882a593Smuzhiyun				status = "disabled";
284*4882a593Smuzhiyun				fsl,adck-max-frequency = <30000000>, <40000000>,
285*4882a593Smuzhiyun							<20000000>;
286*4882a593Smuzhiyun			};
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun			tcon0: timing-controller@4003d000 {
289*4882a593Smuzhiyun				compatible = "fsl,vf610-tcon";
290*4882a593Smuzhiyun				reg = <0x4003d000 0x1000>;
291*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_TCON0>;
292*4882a593Smuzhiyun				clock-names = "ipg";
293*4882a593Smuzhiyun				status = "disabled";
294*4882a593Smuzhiyun			};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun			wdoga5: wdog@4003e000 {
297*4882a593Smuzhiyun				compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
298*4882a593Smuzhiyun				reg = <0x4003e000 0x1000>;
299*4882a593Smuzhiyun				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
300*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_WDT>;
301*4882a593Smuzhiyun				clock-names = "wdog";
302*4882a593Smuzhiyun				status = "disabled";
303*4882a593Smuzhiyun			};
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun			qspi0: spi@40044000 {
306*4882a593Smuzhiyun				#address-cells = <1>;
307*4882a593Smuzhiyun				#size-cells = <0>;
308*4882a593Smuzhiyun				compatible = "fsl,vf610-qspi";
309*4882a593Smuzhiyun				reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
310*4882a593Smuzhiyun				reg-names = "QuadSPI", "QuadSPI-memory";
311*4882a593Smuzhiyun				interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
312*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_QSPI0_EN>,
313*4882a593Smuzhiyun					<&clks VF610_CLK_QSPI0>;
314*4882a593Smuzhiyun				clock-names = "qspi_en", "qspi";
315*4882a593Smuzhiyun				status = "disabled";
316*4882a593Smuzhiyun			};
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun			iomuxc: iomuxc@40048000 {
319*4882a593Smuzhiyun				compatible = "fsl,vf610-iomuxc";
320*4882a593Smuzhiyun				reg = <0x40048000 0x1000>;
321*4882a593Smuzhiyun			};
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun			gpio0: gpio@40049000 {
324*4882a593Smuzhiyun				compatible = "fsl,vf610-gpio";
325*4882a593Smuzhiyun				reg = <0x40049000 0x1000 0x400ff000 0x40>;
326*4882a593Smuzhiyun				gpio-controller;
327*4882a593Smuzhiyun				#gpio-cells = <2>;
328*4882a593Smuzhiyun				interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
329*4882a593Smuzhiyun				interrupt-controller;
330*4882a593Smuzhiyun				#interrupt-cells = <2>;
331*4882a593Smuzhiyun				gpio-ranges = <&iomuxc 0 0 32>;
332*4882a593Smuzhiyun			};
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun			gpio1: gpio@4004a000 {
335*4882a593Smuzhiyun				compatible = "fsl,vf610-gpio";
336*4882a593Smuzhiyun				reg = <0x4004a000 0x1000 0x400ff040 0x40>;
337*4882a593Smuzhiyun				gpio-controller;
338*4882a593Smuzhiyun				#gpio-cells = <2>;
339*4882a593Smuzhiyun				interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
340*4882a593Smuzhiyun				interrupt-controller;
341*4882a593Smuzhiyun				#interrupt-cells = <2>;
342*4882a593Smuzhiyun				gpio-ranges = <&iomuxc 0 32 32>;
343*4882a593Smuzhiyun			};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun			gpio2: gpio@4004b000 {
346*4882a593Smuzhiyun				compatible = "fsl,vf610-gpio";
347*4882a593Smuzhiyun				reg = <0x4004b000 0x1000 0x400ff080 0x40>;
348*4882a593Smuzhiyun				gpio-controller;
349*4882a593Smuzhiyun				#gpio-cells = <2>;
350*4882a593Smuzhiyun				interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
351*4882a593Smuzhiyun				interrupt-controller;
352*4882a593Smuzhiyun				#interrupt-cells = <2>;
353*4882a593Smuzhiyun				gpio-ranges = <&iomuxc 0 64 32>;
354*4882a593Smuzhiyun			};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun			gpio3: gpio@4004c000 {
357*4882a593Smuzhiyun				compatible = "fsl,vf610-gpio";
358*4882a593Smuzhiyun				reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
359*4882a593Smuzhiyun				gpio-controller;
360*4882a593Smuzhiyun				#gpio-cells = <2>;
361*4882a593Smuzhiyun				interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
362*4882a593Smuzhiyun				interrupt-controller;
363*4882a593Smuzhiyun				#interrupt-cells = <2>;
364*4882a593Smuzhiyun				gpio-ranges = <&iomuxc 0 96 32>;
365*4882a593Smuzhiyun			};
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun			gpio4: gpio@4004d000 {
368*4882a593Smuzhiyun				compatible = "fsl,vf610-gpio";
369*4882a593Smuzhiyun				reg = <0x4004d000 0x1000 0x400ff100 0x40>;
370*4882a593Smuzhiyun				gpio-controller;
371*4882a593Smuzhiyun				#gpio-cells = <2>;
372*4882a593Smuzhiyun				interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
373*4882a593Smuzhiyun				interrupt-controller;
374*4882a593Smuzhiyun				#interrupt-cells = <2>;
375*4882a593Smuzhiyun				gpio-ranges = <&iomuxc 0 128 7>;
376*4882a593Smuzhiyun			};
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun			anatop: anatop@40050000 {
379*4882a593Smuzhiyun				compatible = "fsl,vf610-anatop", "syscon";
380*4882a593Smuzhiyun				reg = <0x40050000 0x400>;
381*4882a593Smuzhiyun			};
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun			usbphy0: usbphy@40050800 {
384*4882a593Smuzhiyun				compatible = "fsl,vf610-usbphy";
385*4882a593Smuzhiyun				reg = <0x40050800 0x400>;
386*4882a593Smuzhiyun				interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
387*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_USBPHY0>;
388*4882a593Smuzhiyun				fsl,anatop = <&anatop>;
389*4882a593Smuzhiyun				status = "disabled";
390*4882a593Smuzhiyun			};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun			usbphy1: usbphy@40050c00 {
393*4882a593Smuzhiyun				compatible = "fsl,vf610-usbphy";
394*4882a593Smuzhiyun				reg = <0x40050c00 0x400>;
395*4882a593Smuzhiyun				interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
396*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_USBPHY1>;
397*4882a593Smuzhiyun				fsl,anatop = <&anatop>;
398*4882a593Smuzhiyun				status = "disabled";
399*4882a593Smuzhiyun			};
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun			dcu0: dcu@40058000 {
402*4882a593Smuzhiyun				compatible = "fsl,vf610-dcu";
403*4882a593Smuzhiyun				reg = <0x40058000 0x1200>;
404*4882a593Smuzhiyun				interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
405*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_DCU0>,
406*4882a593Smuzhiyun					<&clks VF610_CLK_DCU0_DIV>;
407*4882a593Smuzhiyun				clock-names = "dcu", "pix";
408*4882a593Smuzhiyun				fsl,tcon = <&tcon0>;
409*4882a593Smuzhiyun				status = "disabled";
410*4882a593Smuzhiyun			};
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun			i2c0: i2c@40066000 {
413*4882a593Smuzhiyun				#address-cells = <1>;
414*4882a593Smuzhiyun				#size-cells = <0>;
415*4882a593Smuzhiyun				compatible = "fsl,vf610-i2c";
416*4882a593Smuzhiyun				reg = <0x40066000 0x1000>;
417*4882a593Smuzhiyun				interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
418*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_I2C0>;
419*4882a593Smuzhiyun				clock-names = "ipg";
420*4882a593Smuzhiyun				dmas = <&edma0 0 50>,
421*4882a593Smuzhiyun					<&edma0 0 51>;
422*4882a593Smuzhiyun				dma-names = "rx","tx";
423*4882a593Smuzhiyun				status = "disabled";
424*4882a593Smuzhiyun			};
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun			i2c1: i2c@40067000 {
427*4882a593Smuzhiyun				#address-cells = <1>;
428*4882a593Smuzhiyun				#size-cells = <0>;
429*4882a593Smuzhiyun				compatible = "fsl,vf610-i2c";
430*4882a593Smuzhiyun				reg = <0x40067000 0x1000>;
431*4882a593Smuzhiyun				interrupts = <72 IRQ_TYPE_LEVEL_HIGH>;
432*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_I2C1>;
433*4882a593Smuzhiyun				clock-names = "ipg";
434*4882a593Smuzhiyun				dmas = <&edma0 0 52>,
435*4882a593Smuzhiyun					<&edma0 0 53>;
436*4882a593Smuzhiyun				dma-names = "rx","tx";
437*4882a593Smuzhiyun				status = "disabled";
438*4882a593Smuzhiyun			};
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun			clks: ccm@4006b000 {
441*4882a593Smuzhiyun				compatible = "fsl,vf610-ccm";
442*4882a593Smuzhiyun				reg = <0x4006b000 0x1000>;
443*4882a593Smuzhiyun				clocks = <&sxosc>, <&fxosc>;
444*4882a593Smuzhiyun				clock-names = "sxosc", "fxosc";
445*4882a593Smuzhiyun				#clock-cells = <1>;
446*4882a593Smuzhiyun			};
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun			usbdev0: usb@40034000 {
449*4882a593Smuzhiyun				compatible = "fsl,vf610-usb", "fsl,imx27-usb";
450*4882a593Smuzhiyun				reg = <0x40034000 0x800>;
451*4882a593Smuzhiyun				interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
452*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_USBC0>;
453*4882a593Smuzhiyun				fsl,usbphy = <&usbphy0>;
454*4882a593Smuzhiyun				fsl,usbmisc = <&usbmisc0 0>;
455*4882a593Smuzhiyun				dr_mode = "peripheral";
456*4882a593Smuzhiyun				status = "disabled";
457*4882a593Smuzhiyun			};
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun			usbmisc0: usb@40034800 {
460*4882a593Smuzhiyun				#index-cells = <1>;
461*4882a593Smuzhiyun				compatible = "fsl,vf610-usbmisc";
462*4882a593Smuzhiyun				reg = <0x40034800 0x200>;
463*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_USBC0>;
464*4882a593Smuzhiyun				status = "disabled";
465*4882a593Smuzhiyun			};
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun			src: src@4006e000 {
468*4882a593Smuzhiyun				compatible = "fsl,vf610-src", "syscon";
469*4882a593Smuzhiyun				reg = <0x4006e000 0x1000>;
470*4882a593Smuzhiyun				interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
471*4882a593Smuzhiyun			};
472*4882a593Smuzhiyun		};
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun		aips1: bus@40080000 {
475*4882a593Smuzhiyun			compatible = "fsl,aips-bus", "simple-bus";
476*4882a593Smuzhiyun			#address-cells = <1>;
477*4882a593Smuzhiyun			#size-cells = <1>;
478*4882a593Smuzhiyun			reg = <0x40080000 0x0007f000>;
479*4882a593Smuzhiyun			ranges;
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun			edma1: dma-controller@40098000 {
482*4882a593Smuzhiyun				#dma-cells = <2>;
483*4882a593Smuzhiyun				compatible = "fsl,vf610-edma";
484*4882a593Smuzhiyun				reg = <0x40098000 0x2000>,
485*4882a593Smuzhiyun					<0x400a1000 0x1000>,
486*4882a593Smuzhiyun					<0x400a2000 0x1000>;
487*4882a593Smuzhiyun				dma-channels = <32>;
488*4882a593Smuzhiyun				interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
489*4882a593Smuzhiyun						<11 IRQ_TYPE_LEVEL_HIGH>;
490*4882a593Smuzhiyun				interrupt-names = "edma-tx", "edma-err";
491*4882a593Smuzhiyun				clock-names = "dmamux0", "dmamux1";
492*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_DMAMUX2>,
493*4882a593Smuzhiyun					<&clks VF610_CLK_DMAMUX3>;
494*4882a593Smuzhiyun				status = "disabled";
495*4882a593Smuzhiyun			};
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun			ocotp: ocotp@400a5000 {
498*4882a593Smuzhiyun				compatible = "fsl,vf610-ocotp", "syscon";
499*4882a593Smuzhiyun				reg = <0x400a5000 0x1000>;
500*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_OCOTP>;
501*4882a593Smuzhiyun			};
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun			snvs0: snvs@400a7000 {
504*4882a593Smuzhiyun			    compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
505*4882a593Smuzhiyun				reg = <0x400a7000 0x2000>;
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun				snvsrtc: snvs-rtc-lp {
508*4882a593Smuzhiyun					compatible = "fsl,sec-v4.0-mon-rtc-lp";
509*4882a593Smuzhiyun					regmap = <&snvs0>;
510*4882a593Smuzhiyun					offset = <0x34>;
511*4882a593Smuzhiyun					interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
512*4882a593Smuzhiyun					clocks = <&clks VF610_CLK_SNVS>;
513*4882a593Smuzhiyun					clock-names = "snvs-rtc";
514*4882a593Smuzhiyun				};
515*4882a593Smuzhiyun			};
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun			uart4: serial@400a9000 {
518*4882a593Smuzhiyun				compatible = "fsl,vf610-lpuart";
519*4882a593Smuzhiyun				reg = <0x400a9000 0x1000>;
520*4882a593Smuzhiyun				interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
521*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_UART4>;
522*4882a593Smuzhiyun				clock-names = "ipg";
523*4882a593Smuzhiyun				status = "disabled";
524*4882a593Smuzhiyun			};
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun			uart5: serial@400aa000 {
527*4882a593Smuzhiyun				compatible = "fsl,vf610-lpuart";
528*4882a593Smuzhiyun				reg = <0x400aa000 0x1000>;
529*4882a593Smuzhiyun				interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
530*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_UART5>;
531*4882a593Smuzhiyun				clock-names = "ipg";
532*4882a593Smuzhiyun				status = "disabled";
533*4882a593Smuzhiyun			};
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun			dspi2: spi@400ac000 {
536*4882a593Smuzhiyun				#address-cells = <1>;
537*4882a593Smuzhiyun				#size-cells = <0>;
538*4882a593Smuzhiyun				compatible = "fsl,vf610-dspi";
539*4882a593Smuzhiyun				reg = <0x400ac000 0x1000>;
540*4882a593Smuzhiyun				interrupts = <69 IRQ_TYPE_LEVEL_HIGH>;
541*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_DSPI2>;
542*4882a593Smuzhiyun				clock-names = "dspi";
543*4882a593Smuzhiyun				spi-num-chipselects = <2>;
544*4882a593Smuzhiyun				dmas = <&edma1 0 10>,
545*4882a593Smuzhiyun					<&edma1 0 11>;
546*4882a593Smuzhiyun				dma-names = "rx", "tx";
547*4882a593Smuzhiyun				status = "disabled";
548*4882a593Smuzhiyun			};
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun			dspi3: spi@400ad000 {
551*4882a593Smuzhiyun				#address-cells = <1>;
552*4882a593Smuzhiyun				#size-cells = <0>;
553*4882a593Smuzhiyun				compatible = "fsl,vf610-dspi";
554*4882a593Smuzhiyun				reg = <0x400ad000 0x1000>;
555*4882a593Smuzhiyun				interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
556*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_DSPI3>;
557*4882a593Smuzhiyun				clock-names = "dspi";
558*4882a593Smuzhiyun				spi-num-chipselects = <2>;
559*4882a593Smuzhiyun				dmas = <&edma1 0 12>,
560*4882a593Smuzhiyun					<&edma1 0 13>;
561*4882a593Smuzhiyun				dma-names = "rx", "tx";
562*4882a593Smuzhiyun				status = "disabled";
563*4882a593Smuzhiyun			};
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun			adc1: adc@400bb000 {
566*4882a593Smuzhiyun				compatible = "fsl,vf610-adc";
567*4882a593Smuzhiyun				reg = <0x400bb000 0x1000>;
568*4882a593Smuzhiyun				interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
569*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_ADC1>;
570*4882a593Smuzhiyun				clock-names = "adc";
571*4882a593Smuzhiyun				#io-channel-cells = <1>;
572*4882a593Smuzhiyun				status = "disabled";
573*4882a593Smuzhiyun				fsl,adck-max-frequency = <30000000>, <40000000>,
574*4882a593Smuzhiyun							<20000000>;
575*4882a593Smuzhiyun			};
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun			esdhc0: esdhc@400b1000 {
578*4882a593Smuzhiyun				compatible = "fsl,imx53-esdhc";
579*4882a593Smuzhiyun				reg = <0x400b1000 0x1000>;
580*4882a593Smuzhiyun				interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
581*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_IPG_BUS>,
582*4882a593Smuzhiyun					<&clks VF610_CLK_PLATFORM_BUS>,
583*4882a593Smuzhiyun					<&clks VF610_CLK_ESDHC0>;
584*4882a593Smuzhiyun				clock-names = "ipg", "ahb", "per";
585*4882a593Smuzhiyun				status = "disabled";
586*4882a593Smuzhiyun			};
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun			esdhc1: esdhc@400b2000 {
589*4882a593Smuzhiyun				compatible = "fsl,imx53-esdhc";
590*4882a593Smuzhiyun				reg = <0x400b2000 0x1000>;
591*4882a593Smuzhiyun				interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
592*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_IPG_BUS>,
593*4882a593Smuzhiyun					<&clks VF610_CLK_PLATFORM_BUS>,
594*4882a593Smuzhiyun					<&clks VF610_CLK_ESDHC1>;
595*4882a593Smuzhiyun				clock-names = "ipg", "ahb", "per";
596*4882a593Smuzhiyun				status = "disabled";
597*4882a593Smuzhiyun			};
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun			usbh1: usb@400b4000 {
600*4882a593Smuzhiyun				compatible = "fsl,vf610-usb", "fsl,imx27-usb";
601*4882a593Smuzhiyun				reg = <0x400b4000 0x800>;
602*4882a593Smuzhiyun				interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
603*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_USBC1>;
604*4882a593Smuzhiyun				fsl,usbphy = <&usbphy1>;
605*4882a593Smuzhiyun				fsl,usbmisc = <&usbmisc1 0>;
606*4882a593Smuzhiyun				dr_mode = "host";
607*4882a593Smuzhiyun				status = "disabled";
608*4882a593Smuzhiyun			};
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun			usbmisc1: usb@400b4800 {
611*4882a593Smuzhiyun				#index-cells = <1>;
612*4882a593Smuzhiyun				compatible = "fsl,vf610-usbmisc";
613*4882a593Smuzhiyun				reg = <0x400b4800 0x200>;
614*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_USBC1>;
615*4882a593Smuzhiyun				status = "disabled";
616*4882a593Smuzhiyun			};
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun			ftm: ftm@400b8000 {
619*4882a593Smuzhiyun				compatible = "fsl,ftm-timer";
620*4882a593Smuzhiyun				reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
621*4882a593Smuzhiyun				interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
622*4882a593Smuzhiyun				clock-names = "ftm-evt", "ftm-src",
623*4882a593Smuzhiyun					"ftm-evt-counter-en", "ftm-src-counter-en";
624*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_FTM2>,
625*4882a593Smuzhiyun					<&clks VF610_CLK_FTM3>,
626*4882a593Smuzhiyun					<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
627*4882a593Smuzhiyun					<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
628*4882a593Smuzhiyun				status = "disabled";
629*4882a593Smuzhiyun			};
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun			qspi1: spi@400c4000 {
632*4882a593Smuzhiyun				#address-cells = <1>;
633*4882a593Smuzhiyun				#size-cells = <0>;
634*4882a593Smuzhiyun				compatible = "fsl,vf610-qspi";
635*4882a593Smuzhiyun				reg = <0x400c4000 0x1000>, <0x50000000 0x10000000>;
636*4882a593Smuzhiyun				reg-names = "QuadSPI", "QuadSPI-memory";
637*4882a593Smuzhiyun				interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
638*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_QSPI1_EN>,
639*4882a593Smuzhiyun					<&clks VF610_CLK_QSPI1>;
640*4882a593Smuzhiyun				clock-names = "qspi_en", "qspi";
641*4882a593Smuzhiyun				status = "disabled";
642*4882a593Smuzhiyun			};
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun			dac0: dac@400cc000 {
645*4882a593Smuzhiyun				compatible = "fsl,vf610-dac";
646*4882a593Smuzhiyun				reg = <0x400cc000 1000>;
647*4882a593Smuzhiyun				interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
648*4882a593Smuzhiyun				clock-names = "dac";
649*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_DAC0>;
650*4882a593Smuzhiyun				status = "disabled";
651*4882a593Smuzhiyun			};
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun			dac1: dac@400cd000 {
654*4882a593Smuzhiyun				compatible = "fsl,vf610-dac";
655*4882a593Smuzhiyun				reg = <0x400cd000 1000>;
656*4882a593Smuzhiyun				interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
657*4882a593Smuzhiyun				clock-names = "dac";
658*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_DAC1>;
659*4882a593Smuzhiyun				status = "disabled";
660*4882a593Smuzhiyun			};
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun			fec0: ethernet@400d0000 {
663*4882a593Smuzhiyun				compatible = "fsl,mvf600-fec";
664*4882a593Smuzhiyun				reg = <0x400d0000 0x1000>;
665*4882a593Smuzhiyun				interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
666*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_ENET0>,
667*4882a593Smuzhiyun					<&clks VF610_CLK_ENET0>,
668*4882a593Smuzhiyun					<&clks VF610_CLK_ENET>;
669*4882a593Smuzhiyun				clock-names = "ipg", "ahb", "ptp";
670*4882a593Smuzhiyun				status = "disabled";
671*4882a593Smuzhiyun			};
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun			fec1: ethernet@400d1000 {
674*4882a593Smuzhiyun				compatible = "fsl,mvf600-fec";
675*4882a593Smuzhiyun				reg = <0x400d1000 0x1000>;
676*4882a593Smuzhiyun				interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
677*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_ENET1>,
678*4882a593Smuzhiyun					<&clks VF610_CLK_ENET1>,
679*4882a593Smuzhiyun					<&clks VF610_CLK_ENET>;
680*4882a593Smuzhiyun				clock-names = "ipg", "ahb", "ptp";
681*4882a593Smuzhiyun				status = "disabled";
682*4882a593Smuzhiyun			};
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun			can1: flexcan@400d4000 {
685*4882a593Smuzhiyun				compatible = "fsl,vf610-flexcan";
686*4882a593Smuzhiyun				reg = <0x400d4000 0x4000>;
687*4882a593Smuzhiyun				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
688*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_FLEXCAN1>,
689*4882a593Smuzhiyun					 <&clks VF610_CLK_FLEXCAN1>;
690*4882a593Smuzhiyun				clock-names = "ipg", "per";
691*4882a593Smuzhiyun				status = "disabled";
692*4882a593Smuzhiyun			};
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun			nfc: nand@400e0000 {
695*4882a593Smuzhiyun				#address-cells = <1>;
696*4882a593Smuzhiyun				#size-cells = <0>;
697*4882a593Smuzhiyun				compatible = "fsl,vf610-nfc";
698*4882a593Smuzhiyun				reg = <0x400e0000 0x4000>;
699*4882a593Smuzhiyun				interrupts = <83 IRQ_TYPE_LEVEL_HIGH>;
700*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_NFC>;
701*4882a593Smuzhiyun				clock-names = "nfc";
702*4882a593Smuzhiyun				status = "disabled";
703*4882a593Smuzhiyun			};
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun			i2c2: i2c@400e6000 {
706*4882a593Smuzhiyun				#address-cells = <1>;
707*4882a593Smuzhiyun				#size-cells = <0>;
708*4882a593Smuzhiyun				compatible = "fsl,vf610-i2c";
709*4882a593Smuzhiyun				reg = <0x400e6000 0x1000>;
710*4882a593Smuzhiyun				interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
711*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_I2C2>;
712*4882a593Smuzhiyun				clock-names = "ipg";
713*4882a593Smuzhiyun				dmas = <&edma0 1 36>,
714*4882a593Smuzhiyun					<&edma0 1 37>;
715*4882a593Smuzhiyun				dma-names = "rx","tx";
716*4882a593Smuzhiyun				status = "disabled";
717*4882a593Smuzhiyun			};
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun			i2c3: i2c@400e7000 {
720*4882a593Smuzhiyun				#address-cells = <1>;
721*4882a593Smuzhiyun				#size-cells = <0>;
722*4882a593Smuzhiyun				compatible = "fsl,vf610-i2c";
723*4882a593Smuzhiyun				reg = <0x400e7000 0x1000>;
724*4882a593Smuzhiyun				interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
725*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_I2C3>;
726*4882a593Smuzhiyun				clock-names = "ipg";
727*4882a593Smuzhiyun				dmas = <&edma0 1 38>,
728*4882a593Smuzhiyun					<&edma0 1 39>;
729*4882a593Smuzhiyun				dma-names = "rx","tx";
730*4882a593Smuzhiyun				status = "disabled";
731*4882a593Smuzhiyun			};
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun			crypto: crypto@400f0000 {
734*4882a593Smuzhiyun				compatible = "fsl,sec-v4.0";
735*4882a593Smuzhiyun				#address-cells = <1>;
736*4882a593Smuzhiyun				#size-cells = <1>;
737*4882a593Smuzhiyun				reg = <0x400f0000 0x9000>;
738*4882a593Smuzhiyun				ranges = <0 0x400f0000 0x9000>;
739*4882a593Smuzhiyun				clocks = <&clks VF610_CLK_CAAM>;
740*4882a593Smuzhiyun				clock-names = "ipg";
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun				sec_jr0: jr0@1000 {
743*4882a593Smuzhiyun					compatible = "fsl,sec-v4.0-job-ring";
744*4882a593Smuzhiyun					reg = <0x1000 0x1000>;
745*4882a593Smuzhiyun					interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
746*4882a593Smuzhiyun				};
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun				sec_jr1: jr1@2000 {
749*4882a593Smuzhiyun					compatible = "fsl,sec-v4.0-job-ring";
750*4882a593Smuzhiyun					reg = <0x2000 0x1000>;
751*4882a593Smuzhiyun					interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
752*4882a593Smuzhiyun				};
753*4882a593Smuzhiyun			};
754*4882a593Smuzhiyun		};
755*4882a593Smuzhiyun	};
756*4882a593Smuzhiyun};
757