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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/marvell/
H A Darmada-ap810-ap0-octa-core.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap810-ap0.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 compatible = "marvell,armada-ap810-octa";
18 compatible = "arm,cortex-a72";
20 enable-method = "psci";
24 compatible = "arm,cortex-a72";
26 enable-method = "psci";
30 compatible = "arm,cortex-a72";
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H A Darmada-ap806-quad.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
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H A Darmada-ap807-quad.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap807.dtsi"
12 compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
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H A Darmada-ap806-dual.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/amazon/
H A Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/hisilicon/
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
12 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a72";
20 cpu-idle-states = <&CPU_PW20>;
21 next-level-cache = <&cluster0_l2>;
22 #cooling-cells = <2>;
27 compatible = "arm,cortex-a72";
30 cpu-idle-states = <&CPU_PW20>;
31 next-level-cache = <&cluster0_l2>;
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H A Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
24 #address-cells = <1>;
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/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc11 ---------
12 The LS1043A integrated multicore processor combines four ARM Cortex-A53
18 - Four 64-bit ARM Cortex-A53 CPUs
19 - 1 MB unified L2 Cache
20 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
22 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
24 - Packet parsing, classification, and distribution (FMan)
25 - Queue management for scheduling, packet sequencing, and congestion
27 - Hardware buffer management for buffer allocation and de-allocation (BMan)
28 - Cryptography acceleration (SEC)
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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Darmada-ap806-quad.dtsi4 * This file is dual-licensed: you can use it either under the terms
47 #include "armada-ap806.dtsi"
51 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
54 #address-cells = <1>;
55 #size-cells = <0>;
59 compatible = "arm,cortex-a72", "arm,armv8";
61 enable-method = "psci";
65 compatible = "arm,cortex-a72", "arm,armv8";
67 enable-method = "psci";
71 compatible = "arm,cortex-a72", "arm,armv8";
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/OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/arm64/
H A Dmapfile.csv10 # to tools/perf/pmu-events/arch/arm64/.
14 #Family-model,Version,Filename,EventType
15 0x00000000410fd030,v1,arm/cortex-a53,core
16 0x00000000420f1000,v1,arm/cortex-a53,core
17 0x00000000410fd070,v1,arm/cortex-a57-a72,core
18 0x00000000410fd080,v1,arm/cortex-a57-a72,core
19 0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
20 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/arm/
H A Djuno-r2.dts9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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/OK3568_Linux_fs/yocto/poky/meta/conf/machine/include/arm/armv8a/
H A Dtune-cortexa72-cortexa53.inc1 DEFAULTTUNE ?= "cortexa72-cortexa53"
3 TUNEVALID[cortexa72-cortexa53] = "Enable big.LITTLE Cortex-A72.Cortex-A53 specific processor optimi…
4 …ARGS .= "${@bb.utils.contains("TUNE_FEATURES", "cortexa72-cortexa53", " -mcpu=cortex-a72.cortex-a5…
5 MACHINEOVERRIDES =. "${@bb.utils.contains("TUNE_FEATURES", "cortexa72-cortexa53", "cortexa72-cortex…
7 require conf/machine/include/arm/arch-armv8a.inc
10 AVAILTUNES += "cortexa72-cortexa53 cortexa72-cortexa53-crypto"
11 ARMPKGARCH:tune-cortexa72-cortexa53 = "cortexa72-cortexa53"
12 ARMPKGARCH:tune-cortexa72-cortexa53-crypto = "cortexa72-cortexa53-crypto"
13 TUNE_FEATURES:tune-cortexa72-cortexa53 = "${TUNE_FEATURES:tune-armv8a-crc} cortexa72-…
14 TUNE_FEATURES:tune-cortexa72-cortexa53-crypto = "${TUNE_FEATURES:tune-cortexa72-cortexa53} c…
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H A Dtune-cortexa72.inc3 TUNEVALID[cortexa72] = "Enable Cortex-A72 specific processor optimizations"
4 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa72', ' -mcpu=cortex-a72', '', d)}"
6 require conf/machine/include/arm/arch-armv8a.inc
9 AVAILTUNES += "cortexa72 cortexa72-crypto"
10 ARMPKGARCH:tune-cortexa72 = "cortexa72"
11 ARMPKGARCH:tune-cortexa72-crypto = "cortexa72"
12 TUNE_FEATURES:tune-cortexa72 = "${TUNE_FEATURES:tune-armv8a-crc} cortexa72"
13 TUNE_FEATURES:tune-cortexa72-crypto = "${TUNE_FEATURES:tune-cortexa72} crypto"
14 PACKAGE_EXTRA_ARCHS:tune-cortexa72 = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc} cortexa72"
15 PACKAGE_EXTRA_ARCHS:tune-cortexa72-crypto = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc-crypto} cortexa7…
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/OK3568_Linux_fs/buildroot/arch/
H A DConfig.in.arm146 bool "arm1136j-s"
152 bool "arm1136jf-s"
159 bool "arm1176jz-s"
165 bool "arm1176jzf-s"
181 bool "cortex-A5"
189 bool "cortex-A7"
197 bool "cortex-A8"
205 bool "cortex-A9"
213 bool "cortex-A12"
221 bool "cortex-A15"
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
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/OK3568_Linux_fs/yocto/meta-clang/classes/
H A Dclang.bbclass2 CCACHE_COMPILERCHECK:toolchain-clang ?= "%compiler% -v"
3 HOST_CC_ARCH:prepend:toolchain-clang = "-target ${HOST_SYS} "
4 CC:toolchain-clang = "${CCACHE}${HOST_PREFIX}clang ${HOST_CC_ARCH}${TOOLCHAIN_OPTIONS}"
5 CXX:toolchain-clang = "${CCACHE}${HOST_PREFIX}clang++ ${HOST_CC_ARCH}${TOOLCHAIN_OPTIONS}"
6 CPP:toolchain-clang = "${CCACHE}${HOST_PREFIX}clang ${HOST_CC_ARCH}${TOOLCHAIN_OPTIONS} -E"
7 CCLD:toolchain-clang = "${CCACHE}${HOST_PREFIX}clang ${HOST_CC_ARCH}${TOOLCHAIN_OPTIONS}"
8 RANLIB:toolchain-clang = "${HOST_PREFIX}llvm-ranlib"
9 AR:toolchain-clang = "${HOST_PREFIX}llvm-ar"
10 NM:toolchain-clang = "${HOST_PREFIX}llvm-nm"
11 OBJDUMP:toolchain-clang = "${HOST_PREFIX}llvm-objdump"
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/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/lib/gcc/aarch64-none-linux-gnu/10.3.1/plugin/include/config/aarch64/
H A Daarch64-cores.def1 /* Copyright (C) 2011-2020 Free Software Foundation, Inc.
31 aarch64-arches.def.
32 FLAGS are the bitwise-or of the traits that apply to that core.
38 ARMv8-A architecture profile.
44 in /proc/cpuinfo. If this is -1, this means it can match any variant. */
46 /* ARMv8-A Architecture Processors. */
49 AARCH64_CORE("cortex-a34", cortexa34, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, corte…
50 AARCH64_CORE("cortex-a35", cortexa35, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, corte…
51 AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, corte…
52 AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, corte…
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3 # Only for s/w models
24 - arm,arm1136-pmu
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/thermal/
H A Dthermal-idle.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-idle.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Daniel Lezcano <daniel.lezcano@linaro.org>
22 const: thermal-idle
24 A thermal-idle node describes the idle cooling device properties to
27 '#cooling-cells':
31 the cooling-maps reference. The first cell is the minimum cooling state
34 duration-us:
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-j7200.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/k3.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
16 interrupt-parent = <&gic500>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <1>;
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H A Dk3-j721e.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/k3.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
16 interrupt-parent = <&gic500>;
17 #address-cells = <2>;
18 #size-cells = <2>;
39 #address-cells = <1>;
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt6797.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <1>;
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/OK3568_Linux_fs/u-boot/board/theobroma-systems/puma_rk3399/
H A DREADME4 The RK3399-Q7 (Puma) is a system-on-module featuring the Rockchip
5 RK3399 in a Qseven-compatible form-factor.
7 RK3399-Q7 features:
8 * CPU: ARMv8 64bit Big-Little architecture,
9 * Big: dual-core Cortex-A72
10 * Little: quad-core Cortex-A53
12 * DRAM: 4GB-128MB dual-channel
22 * Companion Controller: onboard additional Cortex-M0 microcontroller
27 Here is the step-by-step to boot to U-Boot on rk3399.
29 Get the Source and build ATF/Cortex-M0 binaries
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/OK3568_Linux_fs/kernel/arch/arm64/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
168 if $(cc-option,-fpatchable-function-entry=2)
217 ARM 64-bit (AArch64) Linux support.
249 # VA_BITS - PAGE_SHIFT - 3
342 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
369 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
374 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
377 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
383 data cache clean-and-invalidate.
391 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
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