1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun# Copyright 2020 Linaro Ltd. 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: http://devicetree.org/schemas/thermal/thermal-idle.yaml# 6*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: Thermal idle cooling device binding 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Daniel Lezcano <daniel.lezcano@linaro.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun The thermal idle cooling device allows the system to passively 15*4882a593Smuzhiyun mitigate the temperature on the device by injecting idle cycles, 16*4882a593Smuzhiyun forcing it to cool down. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun This binding describes the thermal idle node. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun $nodename: 22*4882a593Smuzhiyun const: thermal-idle 23*4882a593Smuzhiyun description: | 24*4882a593Smuzhiyun A thermal-idle node describes the idle cooling device properties to 25*4882a593Smuzhiyun cool down efficiently the attached thermal zone. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun '#cooling-cells': 28*4882a593Smuzhiyun const: 2 29*4882a593Smuzhiyun description: | 30*4882a593Smuzhiyun Must be 2, in order to specify minimum and maximum cooling state used in 31*4882a593Smuzhiyun the cooling-maps reference. The first cell is the minimum cooling state 32*4882a593Smuzhiyun and the second cell is the maximum cooling state requested. 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun duration-us: 35*4882a593Smuzhiyun description: | 36*4882a593Smuzhiyun The idle duration in microsecond the device should cool down. 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun exit-latency-us: 39*4882a593Smuzhiyun description: | 40*4882a593Smuzhiyun The exit latency constraint in microsecond for the injected idle state 41*4882a593Smuzhiyun for the device. It is the latency constraint to apply when selecting an 42*4882a593Smuzhiyun idle state from among all the present ones. 43*4882a593Smuzhiyun 44*4882a593Smuzhiyunrequired: 45*4882a593Smuzhiyun - '#cooling-cells' 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunadditionalProperties: false 48*4882a593Smuzhiyun 49*4882a593Smuzhiyunexamples: 50*4882a593Smuzhiyun - | 51*4882a593Smuzhiyun #include <dt-bindings/thermal/thermal.h> 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun // Example: Combining idle cooling device on big CPUs with cpufreq cooling device 54*4882a593Smuzhiyun cpus { 55*4882a593Smuzhiyun #address-cells = <2>; 56*4882a593Smuzhiyun #size-cells = <0>; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* ... */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun cpu_b0: cpu@100 { 61*4882a593Smuzhiyun device_type = "cpu"; 62*4882a593Smuzhiyun compatible = "arm,cortex-a72"; 63*4882a593Smuzhiyun reg = <0x0 0x100>; 64*4882a593Smuzhiyun enable-method = "psci"; 65*4882a593Smuzhiyun capacity-dmips-mhz = <1024>; 66*4882a593Smuzhiyun dynamic-power-coefficient = <436>; 67*4882a593Smuzhiyun #cooling-cells = <2>; /* min followed by max */ 68*4882a593Smuzhiyun cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 69*4882a593Smuzhiyun thermal-idle { 70*4882a593Smuzhiyun #cooling-cells = <2>; 71*4882a593Smuzhiyun duration-us = <10000>; 72*4882a593Smuzhiyun exit-latency-us = <500>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun cpu_b1: cpu@101 { 77*4882a593Smuzhiyun device_type = "cpu"; 78*4882a593Smuzhiyun compatible = "arm,cortex-a72"; 79*4882a593Smuzhiyun reg = <0x0 0x101>; 80*4882a593Smuzhiyun enable-method = "psci"; 81*4882a593Smuzhiyun capacity-dmips-mhz = <1024>; 82*4882a593Smuzhiyun dynamic-power-coefficient = <436>; 83*4882a593Smuzhiyun #cooling-cells = <2>; /* min followed by max */ 84*4882a593Smuzhiyun cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 85*4882a593Smuzhiyun thermal-idle { 86*4882a593Smuzhiyun #cooling-cells = <2>; 87*4882a593Smuzhiyun duration-us = <10000>; 88*4882a593Smuzhiyun exit-latency-us = <500>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* ... */ 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* ... */ 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun thermal_zones { 99*4882a593Smuzhiyun cpu_thermal: cpu { 100*4882a593Smuzhiyun polling-delay-passive = <100>; 101*4882a593Smuzhiyun polling-delay = <1000>; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* ... */ 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun trips { 106*4882a593Smuzhiyun cpu_alert0: cpu_alert0 { 107*4882a593Smuzhiyun temperature = <65000>; 108*4882a593Smuzhiyun hysteresis = <2000>; 109*4882a593Smuzhiyun type = "passive"; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun cpu_alert1: cpu_alert1 { 113*4882a593Smuzhiyun temperature = <70000>; 114*4882a593Smuzhiyun hysteresis = <2000>; 115*4882a593Smuzhiyun type = "passive"; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun cpu_alert2: cpu_alert2 { 119*4882a593Smuzhiyun temperature = <75000>; 120*4882a593Smuzhiyun hysteresis = <2000>; 121*4882a593Smuzhiyun type = "passive"; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun cpu_crit: cpu_crit { 125*4882a593Smuzhiyun temperature = <95000>; 126*4882a593Smuzhiyun hysteresis = <2000>; 127*4882a593Smuzhiyun type = "critical"; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun cooling-maps { 132*4882a593Smuzhiyun map0 { 133*4882a593Smuzhiyun trip = <&cpu_alert1>; 134*4882a593Smuzhiyun cooling-device = <&{/cpus/cpu@100/thermal-idle} 0 15 >, 135*4882a593Smuzhiyun <&{/cpus/cpu@101/thermal-idle} 0 15>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun map1 { 139*4882a593Smuzhiyun trip = <&cpu_alert2>; 140*4882a593Smuzhiyun cooling-device = 141*4882a593Smuzhiyun <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 142*4882a593Smuzhiyun <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun }; 147