| /OK3568_Linux_fs/kernel/drivers/clk/qcom/ |
| H A D | clk-regmap.c | 24 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_is_enabled_regmap() local
28 ret = regmap_read(rclk->regmap, rclk->enable_reg, &val); in clk_is_enabled_regmap()
32 if (rclk->enable_is_inverted) in clk_is_enabled_regmap()
33 return (val & rclk->enable_mask) == 0; in clk_is_enabled_regmap()
35 return (val & rclk->enable_mask) != 0; in clk_is_enabled_regmap()
50 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_enable_regmap() local
53 if (rclk->enable_is_inverted) in clk_enable_regmap()
56 val = rclk->enable_mask; in clk_enable_regmap()
58 return regmap_update_bits(rclk->regmap, rclk->enable_reg, in clk_enable_regmap()
59 rclk->enable_mask, val); in clk_enable_regmap()
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| H A D | clk-regmap.h | 36 int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk);
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| /OK3568_Linux_fs/kernel/sound/soc/samsung/ |
| H A D | arndale.c | 27 unsigned long rclk; in arndale_rt5631_hw_params() local
31 rclk = params_rate(params) * rfs; in arndale_rt5631_hw_params()
44 ret = snd_soc_dai_set_sysclk(codec_dai, 0, rclk, SND_SOC_CLOCK_OUT); in arndale_rt5631_hw_params()
60 unsigned int rfs, rclk; in arndale_wm1811_hw_params() local
70 rclk = params_rate(params) * rfs; in arndale_wm1811_hw_params()
80 rclk + 1, SND_SOC_CLOCK_IN); in arndale_wm1811_hw_params()
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| H A D | snow.c | 36 unsigned long int rclk; in snow_card_hw_params() local
76 rclk = params_rate(params) * rfs; in snow_card_hw_params()
80 if ((pll_rate[i] - rclk * psr) <= 2) { in snow_card_hw_params()
87 dev_err(rtd->card->dev, "Unsupported RCLK rate: %lu\n", rclk); in snow_card_hw_params()
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| H A D | s3c-i2s-v2.h | 28 * bridge/break RCLK signal and external Xi2sCDCLK pin.
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/ |
| H A D | ftgmac100.txt | 28 IP clock, and optionally an RMII RCLK gate for the AST2500/AST2600. The
33 - "RCLK": Clock gate for the RMII RCLK
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| /OK3568_Linux_fs/kernel/drivers/slimbus/ |
| H A D | qcom-ctrl.c | 116 struct clk *rclk; member
283 clk_prepare_enable(ctrl->rclk); in qcom_clk_pause_wakeup()
502 ctrl->rclk = devm_clk_get(&pdev->dev, "core"); in qcom_slim_probe()
503 if (IS_ERR(ctrl->rclk)) in qcom_slim_probe()
504 return PTR_ERR(ctrl->rclk); in qcom_slim_probe()
506 ret = clk_set_rate(ctrl->rclk, SLIM_ROOT_FREQ); in qcom_slim_probe()
569 ret = clk_prepare_enable(ctrl->rclk); in qcom_slim_probe()
624 clk_disable_unprepare(ctrl->rclk); in qcom_slim_probe()
639 clk_disable_unprepare(ctrl->rclk); in qcom_slim_remove()
662 clk_disable_unprepare(ctrl->rclk); in qcom_slim_runtime_suspend()
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | aspeed-bmc-portwell-neptune.dts | 85 clock-names = "MACCLK", "RCLK";
94 clock-names = "MACCLK", "RCLK";
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| H A D | aspeed-bmc-facebook-yamp.dts | 42 clock-names = "MACCLK", "RCLK";
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| H A D | aspeed-bmc-intel-s2600wf.dts | 74 clock-names = "MACCLK", "RCLK";
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| H A D | aspeed-bmc-inspur-on5263m5.dts | 82 clock-names = "MACCLK", "RCLK";
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| H A D | aspeed-bmc-arm-stardragon4800-rep2.dts | 97 clock-names = "MACCLK", "RCLK";
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/ |
| H A D | sdhci-msm.txt | 49 "cal" - reference clock for RCLK delay calibration (optional)
50 "sleep" - sleep clock for RCLK delay calibration (optional)
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| H A D | exynos-dw-mshc.txt | 55 * samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode
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| /OK3568_Linux_fs/kernel/drivers/clk/ |
| H A D | clk-ast2600.c | 541 /* MAC1/2 RMII 50MHz RCLK */ in aspeed_g6_clk_probe()
555 /* RMII1 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
563 /* RMII2 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
571 /* MAC1/2 RMII 50MHz RCLK */ in aspeed_g6_clk_probe()
585 /* RMII3 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
593 /* RMII4 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
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| H A D | clk-aspeed.c | 467 /* RMII 50MHz RCLK */ in aspeed_clk_probe()
473 /* RMII1 50MHz (RCLK) output enable */ in aspeed_clk_probe()
481 /* RMII2 50MHz (RCLK) output enable */ in aspeed_clk_probe()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ |
| H A D | baikal,bt1-ccu-pll.yaml | 64 Rclk-+->+---+ | |
70 where Rclk is the reference clock coming from XTAL, NR - reference clock
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| /OK3568_Linux_fs/kernel/include/dt-bindings/sound/ |
| H A D | samsung-i2s.h | 11 #define CLK_I2S_RCLK_PSR 2 /* the RCLK prescaler divider clock
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| /OK3568_Linux_fs/kernel/drivers/media/i2c/it66353/ |
| H A D | it66353.c | 1779 // if CEC is enabled, we should have a accurate RCLK. in _sw_init()
1785 cec_timer_unit = it66353_gdev.vars.RCLK / (16*10); in _sw_init()
1891 // To have accurate RCLK,
1899 u32 sum, rclk_tmp, rclk, rddata; in it66353_cal_rclk() local
1914 rclk = sum / 100; in it66353_cal_rclk()
1916 DEBUG("RCLK=%d kHz\r\n\r\n", rclk); in it66353_cal_rclk()
1918 timer_int = rclk / 1000; in it66353_cal_rclk()
1919 timer_flt = (rclk - timer_int * 1000) * 256 / 1000; in it66353_cal_rclk()
1924 rclk_tmp = (rclk) * (1 << RCLKFreqSel); in it66353_cal_rclk()
1941 it66353_gdev.vars.RCLK = rclk; in it66353_cal_rclk()
[all …]
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/qcom/ |
| H A D | qcs404-evb.dtsi | 260 rclk {
285 rclk {
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| /OK3568_Linux_fs/kernel/drivers/media/i2c/ |
| H A D | it6616.c | 526 u32 rclk; member
2194 it6616_mipi_tx_set_bits(mipi, 0xE0, 0x80, 0x80); // Enable RCLK 100ms count in it6616_mipi_tx_calc_rclk()
2196 it6616_mipi_tx_set_bits(mipi, 0xE0, 0x80, 0x00); // Disable RCLK 100ms count in it6616_mipi_tx_calc_rclk()
2207 dev_dbg(dev, "mipi rclk = %d.%d MHz", it6616->tx_rclk / 1000, in it6616_mipi_tx_calc_rclk()
2268 u32 rddata, rclk, sum = 0; in it6616_hdmi_rx_calc_rclk() local
2286 rclk = sum / TIMER_100MS; in it6616_hdmi_rx_calc_rclk()
2288 dev_dbg(dev, "RCLK=%u KHz\n", rclk); in it6616_hdmi_rx_calc_rclk()
2290 t1usint = rclk / 1000; in it6616_hdmi_rx_calc_rclk()
2291 t1usflt = (rclk / 1000 - t1usint) * 256; in it6616_hdmi_rx_calc_rclk()
2295 it6616->rclk = rclk; in it6616_hdmi_rx_calc_rclk()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/clk/renesas/ |
| H A D | rcar-gen3-cpg.c | 32 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
382 #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
645 /* Select parent clock of RCLK by MD28 */ in rcar_gen3_cpg_clk_register()
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| /OK3568_Linux_fs/kernel/drivers/net/ethernet/faraday/ |
| H A D | ftgmac100.c | 93 struct clk *rclk; member
1735 /* RCLK is for RMII, typically used for NCSI. Optional because it's not in ftgmac100_setup_clk()
1739 priv->rclk = devm_clk_get_optional(priv->dev, "RCLK"); in ftgmac100_setup_clk()
1740 rc = clk_prepare_enable(priv->rclk); in ftgmac100_setup_clk()
1930 clk_disable_unprepare(priv->rclk); in ftgmac100_probe()
1958 clk_disable_unprepare(priv->rclk); in ftgmac100_remove()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/ |
| H A D | cadence-quadspi.txt | 20 - cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
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| /OK3568_Linux_fs/kernel/arch/mips/alchemy/common/ |
| H A D | clock.c | 34 * later models it's called RCLK.
340 * L/RCLK = periph_clk / (divisor + 1) in alchemy_clk_setup_lrclk()
342 * on later models it's called RCLK, but it's the same thing. in alchemy_clk_setup_lrclk()
1086 /* L/RCLK: external static bus clock for synchronous mode */ in alchemy_clk_init()
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