1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ALSA Soc Audio Layer - S3C_I2SV2 I2S driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2007 Simtec Electronics 6*4882a593Smuzhiyun * http://armlinux.simtec.co.uk/ 7*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* This code is the core support for the I2S block found in a number of 11*4882a593Smuzhiyun * Samsung SoC devices which is unofficially named I2S-V2. Currently the 12*4882a593Smuzhiyun * S3C2412 and the S3C64XX series use this block to provide 1 or 2 I2S 13*4882a593Smuzhiyun * channels via configurable GPIO. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef __SND_SOC_S3C24XX_S3C_I2SV2_I2S_H 17*4882a593Smuzhiyun #define __SND_SOC_S3C24XX_S3C_I2SV2_I2S_H __FILE__ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define S3C_I2SV2_DIV_BCLK (1) 20*4882a593Smuzhiyun #define S3C_I2SV2_DIV_RCLK (2) 21*4882a593Smuzhiyun #define S3C_I2SV2_DIV_PRESCALER (3) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define S3C_I2SV2_CLKSRC_PCLK 0 24*4882a593Smuzhiyun #define S3C_I2SV2_CLKSRC_AUDIOBUS 1 25*4882a593Smuzhiyun #define S3C_I2SV2_CLKSRC_CDCLK 2 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Set this flag for I2S controllers that have the bit IISMOD[12] 28*4882a593Smuzhiyun * bridge/break RCLK signal and external Xi2sCDCLK pin. 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun #define S3C_FEATURE_CDCLKCON (1 << 0) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /** 33*4882a593Smuzhiyun * struct s3c_i2sv2_info - S3C I2S-V2 information 34*4882a593Smuzhiyun * @dev: The parent device passed to use from the probe. 35*4882a593Smuzhiyun * @regs: The pointer to the device registe block. 36*4882a593Smuzhiyun * @feature: Set of bit-flags indicating features of the controller. 37*4882a593Smuzhiyun * @master: True if the I2S core is the I2S bit clock master. 38*4882a593Smuzhiyun * @dma_playback: DMA information for playback channel. 39*4882a593Smuzhiyun * @dma_capture: DMA information for capture channel. 40*4882a593Smuzhiyun * @suspend_iismod: PM save for the IISMOD register. 41*4882a593Smuzhiyun * @suspend_iiscon: PM save for the IISCON register. 42*4882a593Smuzhiyun * @suspend_iispsr: PM save for the IISPSR register. 43*4882a593Smuzhiyun * 44*4882a593Smuzhiyun * This is the private codec state for the hardware associated with an 45*4882a593Smuzhiyun * I2S channel such as the register mappings and clock sources. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun struct s3c_i2sv2_info { 48*4882a593Smuzhiyun struct device *dev; 49*4882a593Smuzhiyun void __iomem *regs; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun u32 feature; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct clk *iis_pclk; 54*4882a593Smuzhiyun struct clk *iis_cclk; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun unsigned char master; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun struct snd_dmaengine_dai_dma_data *dma_playback; 59*4882a593Smuzhiyun struct snd_dmaengine_dai_dma_data *dma_capture; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun u32 suspend_iismod; 62*4882a593Smuzhiyun u32 suspend_iiscon; 63*4882a593Smuzhiyun u32 suspend_iispsr; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun unsigned long base; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun extern struct clk *s3c_i2sv2_get_clock(struct snd_soc_dai *cpu_dai); 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct s3c_i2sv2_rate_calc { 71*4882a593Smuzhiyun unsigned int clk_div; /* for prescaler */ 72*4882a593Smuzhiyun unsigned int fs_div; /* for root frame clock */ 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun extern int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info, 76*4882a593Smuzhiyun unsigned int *fstab, 77*4882a593Smuzhiyun unsigned int rate, struct clk *clk); 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /** 80*4882a593Smuzhiyun * s3c_i2sv2_probe - probe for i2s device helper 81*4882a593Smuzhiyun * @dai: The ASoC DAI structure supplied to the original probe. 82*4882a593Smuzhiyun * @i2s: Our local i2s structure to fill in. 83*4882a593Smuzhiyun * @base: The base address for the registers. 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun extern int s3c_i2sv2_probe(struct snd_soc_dai *dai, 86*4882a593Smuzhiyun struct s3c_i2sv2_info *i2s); 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /** 89*4882a593Smuzhiyun * s3c_i2sv2_cleanup - cleanup resources allocated in s3c_i2sv2_probe 90*4882a593Smuzhiyun * @dai: The ASoC DAI structure supplied to the original probe. 91*4882a593Smuzhiyun * @i2s: Our local i2s structure to fill in. 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun extern void s3c_i2sv2_cleanup(struct snd_soc_dai *dai, 94*4882a593Smuzhiyun struct s3c_i2sv2_info *i2s); 95*4882a593Smuzhiyun /** 96*4882a593Smuzhiyun * s3c_i2sv2_register_component - register component and dai with soc core 97*4882a593Smuzhiyun * @dev: DAI device 98*4882a593Smuzhiyun * @id: DAI ID 99*4882a593Smuzhiyun * @drv: The driver structure to register 100*4882a593Smuzhiyun * 101*4882a593Smuzhiyun * Fill in any missing fields and then register the given dai with the 102*4882a593Smuzhiyun * soc core. 103*4882a593Smuzhiyun */ 104*4882a593Smuzhiyun extern int s3c_i2sv2_register_component(struct device *dev, int id, 105*4882a593Smuzhiyun const struct snd_soc_component_driver *cmp_drv, 106*4882a593Smuzhiyun struct snd_soc_dai_driver *dai_drv); 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #endif /* __SND_SOC_S3C24XX_S3C_I2SV2_I2S_H */ 109