Lines Matching full:rclk
1779 // if CEC is enabled, we should have a accurate RCLK. in _sw_init()
1785 cec_timer_unit = it66353_gdev.vars.RCLK / (16*10); in _sw_init()
1891 // To have accurate RCLK,
1899 u32 sum, rclk_tmp, rclk, rddata; in it66353_cal_rclk() local
1914 rclk = sum / 100; in it66353_cal_rclk()
1916 DEBUG("RCLK=%d kHz\r\n\r\n", rclk); in it66353_cal_rclk()
1918 timer_int = rclk / 1000; in it66353_cal_rclk()
1919 timer_flt = (rclk - timer_int * 1000) * 256 / 1000; in it66353_cal_rclk()
1924 rclk_tmp = (rclk) * (1 << RCLKFreqSel); in it66353_cal_rclk()
1941 it66353_gdev.vars.RCLK = rclk; in it66353_cal_rclk()
1955 // RCLK=20000 kHz in it66353_init_rclk()
1962 it66353_gdev.vars.RCLK = 20000; in it66353_init_rclk()
1965 // RCLK=19569 kHz in it66353_init_rclk()
1972 it66353_gdev.vars.RCLK = 19569; in it66353_init_rclk()
1975 // RCLK=18562 kHz in it66353_init_rclk()
1982 it66353_gdev.vars.RCLK = 18562; in it66353_init_rclk()
2102 tmds_clk = it66353_gdev.vars.RCLK * 256 * wdog_clk_div / tmds_clk_speed; in it66353_get_rx_vclk()
2117 tmds_clk = it66353_gdev.vars.RCLK * 256 * wdog_clk_div / tmds_clk_speed; in it66353_get_rx_vclk()