1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _DT_BINDINGS_SAMSUNG_I2S_H 3*4882a593Smuzhiyun #define _DT_BINDINGS_SAMSUNG_I2S_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define CLK_I2S_RCLK_SRC 1 /* the RCLKSRC mux clock (corresponding to 8*4882a593Smuzhiyun * RCLKSRC bit in IISMOD register) 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CLK_I2S_RCLK_PSR 2 /* the RCLK prescaler divider clock 12*4882a593Smuzhiyun * (corresponding to the IISPSR register) 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #endif /* _DT_BINDINGS_SAMSUNG_I2S_H */ 16