| /OK3568_Linux_fs/u-boot/arch/arm/dts/ |
| H A D | imx6dl-pinfunc.h | 17 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
20 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
21 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
22 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
23 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
24 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
25 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
26 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | imx6dl-pinfunc.h | 13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
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| H A D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
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| H A D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
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| H A D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
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| H A D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | sama5_matrix.h | 14 u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */
15 u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */
16 u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */
17 u32 res1[20]; /* 0x100 ~ 0x14c */
18 u32 meier; /* 0x150: Master Error Interrupt Enable Register */
19 u32 meidr; /* 0x154: Master Error Interrupt Disable Register */
20 u32 meimr; /* 0x158: Master Error Interrupt Mask Register */
21 u32 mesr; /* 0x15c: Master Error Status Register */
22 u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */
23 u32 res2[17]; /* 0x1A0 ~ 0x1E0 */
[all …]
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| /OK3568_Linux_fs/kernel/drivers/video/rockchip/rve/include/ |
| H A D | rve_reg.h | 8 #define RVE_SWREG0_IVE_VERSION 0x000
9 #define RVE_SWREG1_IVE_IRQ 0x004
10 #define RVE_SWREG2_IRQ_CTRL 0x008
11 #define RVE_SWREG3_IVE_IDLE_PRC_STA 0x00c
12 #define RVE_SWREG4_IVE_FORCE_IDLE_WBASE 0x010
13 #define RVE_SWREG5_IVE_IDLE_CTRL 0x014
14 #define RVE_SWREG6_IVE_WORK_STA 0x018
15 #define RVE_SWREG7_IVE_SWAP 0x01c
18 #define RVE_SWLTB0_START_BASE 0x100
19 #define RVE_SWLTB1_CTRL 0x104
[all …]
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/ |
| H A D | fsl,imx8mn-pinctrl.yaml | 72 reg = <0x30330000 0x10000>;
76 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
77 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
|
| H A D | fsl,imx8mm-pinctrl.yaml | 72 reg = <0x30330000 0x10000>;
76 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
77 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
|
| /OK3568_Linux_fs/kernel/include/linux/bcma/ |
| H A D | bcma_driver_gmac_cmn.h | 7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpucfg.h | 18 u32 rst; /* base + 0x0 */
19 u32 ctrl; /* base + 0x4 */
20 u32 status; /* base + 0x8 */
21 u8 res[0x34]; /* base + 0xc */
25 u8 res0[0x40]; /* 0x000 */
26 struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */
27 u8 res1[0x44]; /* 0x140 */
28 u32 gen_ctrl; /* 0x184 */
29 u32 l2_status; /* 0x188 */
30 u8 res2[0x4]; /* 0x18c */
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | grf_rk322x.h | 34 unsigned int reserved2[(0x100 - 0x50) / 4 - 1];
39 unsigned int reserved3[(0x200 - 0x13c) / 4 - 1];
44 unsigned int reserved4[(0x400 - 0x23c) / 4 - 1];
46 unsigned int reserved5[(0x480 - 0x418) / 4 - 1];
49 unsigned int reserved6[(0x500 - 0x48c) / 4 - 1];
53 unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1];
55 unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
57 unsigned int reserved10[(0x680 - 0x604) / 4 - 1];
59 unsigned int reserved11[(0x690 - 0x684) / 4 - 1];
61 unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1];
[all …]
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| /OK3568_Linux_fs/u-boot/include/ |
| H A D | fsl_sfp.h | 38 u32 ospr; /* 0x200 */
39 u32 ospr1; /* 0x204 */
41 u32 fswpr; /* 0x218 FSL Section Write Protect */
42 u32 fsl_uid; /* 0x21c FSL UID 0 */
43 u32 fsl_uid_1; /* 0x220 FSL UID 0 */
45 u32 srk_hash[8]; /* 0x254 Super Root Key Hash */
46 u32 oem_uid; /* 0x274 OEM UID 0*/
47 u32 oem_uid_1; /* 0x278 OEM UID 1*/
48 u32 oem_uid_2; /* 0x27c OEM UID 2*/
49 u32 oem_uid_3; /* 0x280 OEM UID 3*/
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra124/ |
| H A D | mc.h | 14 u32 reserved0[4]; /* offset 0x00 - 0x0C */
15 u32 mc_smmu_config; /* offset 0x10 */
16 u32 mc_smmu_tlb_config; /* offset 0x14 */
17 u32 mc_smmu_ptc_config; /* offset 0x18 */
18 u32 mc_smmu_ptb_asid; /* offset 0x1C */
19 u32 mc_smmu_ptb_data; /* offset 0x20 */
20 u32 reserved1[3]; /* offset 0x24 - 0x2C */
21 u32 mc_smmu_tlb_flush; /* offset 0x30 */
22 u32 mc_smmu_ptc_flush; /* offset 0x34 */
23 u32 reserved2[6]; /* offset 0x38 - 0x4C */
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra210/ |
| H A D | mc.h | 14 u32 reserved0[4]; /* offset 0x00 - 0x0C */
15 u32 mc_smmu_config; /* offset 0x10 */
16 u32 mc_smmu_tlb_config; /* offset 0x14 */
17 u32 mc_smmu_ptc_config; /* offset 0x18 */
18 u32 mc_smmu_ptb_asid; /* offset 0x1C */
19 u32 mc_smmu_ptb_data; /* offset 0x20 */
20 u32 reserved1[3]; /* offset 0x24 - 0x2C */
21 u32 mc_smmu_tlb_flush; /* offset 0x30 */
22 u32 mc_smmu_ptc_flush; /* offset 0x34 */
23 u32 reserved2[6]; /* offset 0x38 - 0x4C */
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-zynqmp/ |
| H A D | hardware.h | 11 #define ZYNQ_GEM_BASEADDR0 0xFF0B0000
12 #define ZYNQ_GEM_BASEADDR1 0xFF0C0000
13 #define ZYNQ_GEM_BASEADDR2 0xFF0D0000
14 #define ZYNQ_GEM_BASEADDR3 0xFF0E0000
16 #define ZYNQ_I2C_BASEADDR0 0xFF020000
17 #define ZYNQ_I2C_BASEADDR1 0xFF030000
19 #define ARASAN_NAND_BASEADDR 0xFF100000
21 #define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000
22 #define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000
24 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
[all …]
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| /OK3568_Linux_fs/kernel/sound/soc/fsl/ |
| H A D | fsl_audmix.h | 15 #define FSL_AUDMIX_CTR 0x200 /* Control */
16 #define FSL_AUDMIX_STR 0x204 /* Status */
18 #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */
19 #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */
20 #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
21 #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
22 #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */
23 #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
24 #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */
26 #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */
[all …]
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/rf/halrf_8852b/ |
| H A D | halrf_efuse_8852b.h | 31 EFUSE_INFO_RF_BOARD_OPTION_8852B_ADDR = 0x2c1,
32 EFUSE_INFO_RF_RFE_8852B_ADDR = 0x2ca,
33 EFUSE_INFO_RF_CHAN_PLAN_8852B_ADDR = 0x2b8,
34 EFUSE_INFO_RF_XTAL_8852B_ADDR = 0x2b9,
35 EFUSE_INFO_RF_THERMAL_A_8852B_ADDR = 0x2d0,
36 EFUSE_INFO_RF_THERMAL_B_8852B_ADDR = 0x2d1,
37 EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1_8852B_ADDR = 0x210,
38 EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2_8852B_ADDR = 0x211,
39 EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3_8852B_ADDR = 0x212,
40 EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4_8852B_ADDR = 0x213,
[all …]
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/rf/halrf_8852b/ |
| H A D | halrf_efuse_8852b.h | 31 EFUSE_INFO_RF_BOARD_OPTION_8852B_ADDR = 0x2c1,
32 EFUSE_INFO_RF_RFE_8852B_ADDR = 0x2ca,
33 EFUSE_INFO_RF_CHAN_PLAN_8852B_ADDR = 0x2b8,
34 EFUSE_INFO_RF_XTAL_8852B_ADDR = 0x2b9,
35 EFUSE_INFO_RF_THERMAL_A_8852B_ADDR = 0x2d0,
36 EFUSE_INFO_RF_THERMAL_B_8852B_ADDR = 0x2d1,
37 EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1_8852B_ADDR = 0x210,
38 EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2_8852B_ADDR = 0x211,
39 EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3_8852B_ADDR = 0x212,
40 EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4_8852B_ADDR = 0x213,
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/ |
| H A D | nwl-dsi.h | 12 #define NWL_DSI_CFG_NUM_LANES 0x0
13 #define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4
14 #define NWL_DSI_CFG_T_PRE 0x8
15 #define NWL_DSI_CFG_T_POST 0xc
16 #define NWL_DSI_CFG_TX_GAP 0x10
17 #define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14
18 #define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18
19 #define NWL_DSI_CFG_HTX_TO_COUNT 0x1c
20 #define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20
21 #define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24
[all …]
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| /OK3568_Linux_fs/kernel/drivers/input/mouse/ |
| H A D | inport.c | 32 #define INPORT_BASE 0x23c
35 #define INPORT_CONTROL_PORT INPORT_BASE + 0
39 #define INPORT_REG_BTNS 0x00
40 #define INPORT_REG_X 0x01
41 #define INPORT_REG_Y 0x02
42 #define INPORT_REG_MODE 0x07
43 #define INPORT_RESET 0x80
47 #define INPORT_VENDOR 0x0002
48 #define INPORT_SPEED_30HZ 0x01
49 #define INPORT_SPEED_50HZ 0x02
[all …]
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| H A D | logibm.c | 34 #define LOGIBM_BASE 0x23c
37 #define LOGIBM_DATA_PORT LOGIBM_BASE + 0
42 #define LOGIBM_ENABLE_IRQ 0x00
43 #define LOGIBM_DISABLE_IRQ 0x10
44 #define LOGIBM_READ_X_LOW 0x80
45 #define LOGIBM_READ_X_HIGH 0xa0
46 #define LOGIBM_READ_Y_LOW 0xc0
47 #define LOGIBM_READ_Y_HIGH 0xe0
49 #define LOGIBM_DEFAULT_MODE 0x90
50 #define LOGIBM_CONFIG_BYTE 0x91
[all …]
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| /OK3568_Linux_fs/kernel/arch/powerpc/boot/ |
| H A D | wii-head.S | 29 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
43 li 8, 0
44 mtspr 0x210, 8 /* IBAT0U */
45 mtspr 0x212, 8 /* IBAT1U */
46 mtspr 0x214, 8 /* IBAT2U */
47 mtspr 0x216, 8 /* IBAT3U */
48 mtspr 0x218, 8 /* DBAT0U */
49 mtspr 0x21a, 8 /* DBAT1U */
50 mtspr 0x21c, 8 /* DBAT2U */
51 mtspr 0x21e, 8 /* DBAT3U */
[all …]
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