1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _ASM_ARCH_GRF_RK322X_H 7*4882a593Smuzhiyun #define _ASM_ARCH_GRF_RK322X_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct rk322x_grf { 12*4882a593Smuzhiyun unsigned int gpio0a_iomux; 13*4882a593Smuzhiyun unsigned int gpio0b_iomux; 14*4882a593Smuzhiyun unsigned int gpio0c_iomux; 15*4882a593Smuzhiyun unsigned int gpio0d_iomux; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun unsigned int gpio1a_iomux; 18*4882a593Smuzhiyun unsigned int gpio1b_iomux; 19*4882a593Smuzhiyun unsigned int gpio1c_iomux; 20*4882a593Smuzhiyun unsigned int gpio1d_iomux; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun unsigned int gpio2a_iomux; 23*4882a593Smuzhiyun unsigned int gpio2b_iomux; 24*4882a593Smuzhiyun unsigned int gpio2c_iomux; 25*4882a593Smuzhiyun unsigned int gpio2d_iomux; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun unsigned int gpio3a_iomux; 28*4882a593Smuzhiyun unsigned int gpio3b_iomux; 29*4882a593Smuzhiyun unsigned int gpio3c_iomux; 30*4882a593Smuzhiyun unsigned int gpio3d_iomux; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun unsigned int reserved1[4]; 33*4882a593Smuzhiyun unsigned int con_iomux; 34*4882a593Smuzhiyun unsigned int reserved2[(0x100 - 0x50) / 4 - 1]; 35*4882a593Smuzhiyun unsigned int gpio0_p[4]; 36*4882a593Smuzhiyun unsigned int gpio1_p[4]; 37*4882a593Smuzhiyun unsigned int gpio2_p[4]; 38*4882a593Smuzhiyun unsigned int gpio3_p[4]; 39*4882a593Smuzhiyun unsigned int reserved3[(0x200 - 0x13c) / 4 - 1]; 40*4882a593Smuzhiyun unsigned int gpio0_e[4]; 41*4882a593Smuzhiyun unsigned int gpio1_e[4]; 42*4882a593Smuzhiyun unsigned int gpio2_e[4]; 43*4882a593Smuzhiyun unsigned int gpio3_e[4]; 44*4882a593Smuzhiyun unsigned int reserved4[(0x400 - 0x23c) / 4 - 1]; 45*4882a593Smuzhiyun unsigned int soc_con[7]; 46*4882a593Smuzhiyun unsigned int reserved5[(0x480 - 0x418) / 4 - 1]; 47*4882a593Smuzhiyun unsigned int soc_status[3]; 48*4882a593Smuzhiyun unsigned int chip_id; 49*4882a593Smuzhiyun unsigned int reserved6[(0x500 - 0x48c) / 4 - 1]; 50*4882a593Smuzhiyun unsigned int cpu_con[4]; 51*4882a593Smuzhiyun unsigned int reserved7[4]; 52*4882a593Smuzhiyun unsigned int cpu_status[2]; 53*4882a593Smuzhiyun unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1]; 54*4882a593Smuzhiyun unsigned int os_reg[8]; 55*4882a593Smuzhiyun unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1]; 56*4882a593Smuzhiyun unsigned int ddrc_stat; 57*4882a593Smuzhiyun unsigned int reserved10[(0x680 - 0x604) / 4 - 1]; 58*4882a593Smuzhiyun unsigned int sig_detect_con[2]; 59*4882a593Smuzhiyun unsigned int reserved11[(0x690 - 0x684) / 4 - 1]; 60*4882a593Smuzhiyun unsigned int sig_detect_status[2]; 61*4882a593Smuzhiyun unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1]; 62*4882a593Smuzhiyun unsigned int sig_detect_clr[2]; 63*4882a593Smuzhiyun unsigned int reserved13[(0x6b0 - 0x6a4) / 4 - 1]; 64*4882a593Smuzhiyun unsigned int emmc_det; 65*4882a593Smuzhiyun unsigned int reserved14[(0x700 - 0x6b0) / 4 - 1]; 66*4882a593Smuzhiyun unsigned int host0_con[3]; 67*4882a593Smuzhiyun unsigned int reserved15; 68*4882a593Smuzhiyun unsigned int host1_con[3]; 69*4882a593Smuzhiyun unsigned int reserved16; 70*4882a593Smuzhiyun unsigned int host2_con[3]; 71*4882a593Smuzhiyun unsigned int reserved17[(0x760 - 0x728) / 4 - 1]; 72*4882a593Smuzhiyun unsigned int usbphy0_con[27]; 73*4882a593Smuzhiyun unsigned int reserved18[(0x800 - 0x7c8) / 4 - 1]; 74*4882a593Smuzhiyun unsigned int usbphy1_con[27]; 75*4882a593Smuzhiyun unsigned int reserved19[(0x880 - 0x868) / 4 - 1]; 76*4882a593Smuzhiyun unsigned int otg_con0; 77*4882a593Smuzhiyun unsigned int uoc_status0; 78*4882a593Smuzhiyun unsigned int reserved20[(0x900 - 0x884) / 4 - 1]; 79*4882a593Smuzhiyun unsigned int mac_con[2]; 80*4882a593Smuzhiyun unsigned int reserved21[(0xb00 - 0x904) / 4 - 1]; 81*4882a593Smuzhiyun unsigned int macphy_con[4]; 82*4882a593Smuzhiyun unsigned int macphy_status; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun check_member(rk322x_grf, ddrc_stat, 0x604); 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun struct rk322x_sgrf { 87*4882a593Smuzhiyun unsigned int soc_con[11]; 88*4882a593Smuzhiyun unsigned int busdmac_con[4]; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* GRF_MACPHY_CON0 */ 92*4882a593Smuzhiyun enum { 93*4882a593Smuzhiyun MACPHY_CFG_ENABLE_SHIFT = 0, 94*4882a593Smuzhiyun MACPHY_CFG_ENABLE_MASK = 1 << MACPHY_CFG_ENABLE_SHIFT, 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun #endif 97