1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * NXP AUDMIX ALSA SoC Digital Audio Interface (DAI) driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2017 NXP 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __FSL_AUDMIX_H 9*4882a593Smuzhiyun #define __FSL_AUDMIX_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define FSL_AUDMIX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 12*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE |\ 13*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S32_LE) 14*4882a593Smuzhiyun /* AUDMIX Registers */ 15*4882a593Smuzhiyun #define FSL_AUDMIX_CTR 0x200 /* Control */ 16*4882a593Smuzhiyun #define FSL_AUDMIX_STR 0x204 /* Status */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */ 19*4882a593Smuzhiyun #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */ 20*4882a593Smuzhiyun #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */ 21*4882a593Smuzhiyun #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */ 22*4882a593Smuzhiyun #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */ 23*4882a593Smuzhiyun #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */ 24*4882a593Smuzhiyun #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */ 27*4882a593Smuzhiyun #define FSL_AUDMIX_ATIVAL1 0x22c /* Attenuation Initial Value */ 28*4882a593Smuzhiyun #define FSL_AUDMIX_ATSTPUP1 0x230 /* Attenuation step up factor */ 29*4882a593Smuzhiyun #define FSL_AUDMIX_ATSTPDN1 0x234 /* Attenuation step down factor */ 30*4882a593Smuzhiyun #define FSL_AUDMIX_ATSTPTGT1 0x238 /* Attenuation step target */ 31*4882a593Smuzhiyun #define FSL_AUDMIX_ATTNVAL1 0x23c /* Attenuation Value */ 32*4882a593Smuzhiyun #define FSL_AUDMIX_ATSTP1 0x240 /* Attenuation step number */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* AUDMIX Control Register */ 35*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_MIXCLK_SHIFT 0 36*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_MIXCLK_MASK BIT(FSL_AUDMIX_CTR_MIXCLK_SHIFT) 37*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_MIXCLK(i) ((i) << FSL_AUDMIX_CTR_MIXCLK_SHIFT) 38*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_OUTSRC_SHIFT 1 39*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_OUTSRC_MASK (0x3 << FSL_AUDMIX_CTR_OUTSRC_SHIFT) 40*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_OUTSRC(i) (((i) << FSL_AUDMIX_CTR_OUTSRC_SHIFT)\ 41*4882a593Smuzhiyun & FSL_AUDMIX_CTR_OUTSRC_MASK) 42*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_OUTWIDTH_SHIFT 3 43*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_OUTWIDTH_MASK (0x7 << FSL_AUDMIX_CTR_OUTWIDTH_SHIFT) 44*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_OUTWIDTH(i) (((i) << FSL_AUDMIX_CTR_OUTWIDTH_SHIFT)\ 45*4882a593Smuzhiyun & FSL_AUDMIX_CTR_OUTWIDTH_MASK) 46*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_OUTCKPOL_SHIFT 6 47*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_OUTCKPOL_MASK BIT(FSL_AUDMIX_CTR_OUTCKPOL_SHIFT) 48*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_OUTCKPOL(i) ((i) << FSL_AUDMIX_CTR_OUTCKPOL_SHIFT) 49*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_MASKRTDF_SHIFT 7 50*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_MASKRTDF_MASK BIT(FSL_AUDMIX_CTR_MASKRTDF_SHIFT) 51*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_MASKRTDF(i) ((i) << FSL_AUDMIX_CTR_MASKRTDF_SHIFT) 52*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_MASKCKDF_SHIFT 8 53*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_MASKCKDF_MASK BIT(FSL_AUDMIX_CTR_MASKCKDF_SHIFT) 54*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_MASKCKDF(i) ((i) << FSL_AUDMIX_CTR_MASKCKDF_SHIFT) 55*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_SYNCMODE_SHIFT 9 56*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_SYNCMODE_MASK BIT(FSL_AUDMIX_CTR_SYNCMODE_SHIFT) 57*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_SYNCMODE(i) ((i) << FSL_AUDMIX_CTR_SYNCMODE_SHIFT) 58*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_SYNCSRC_SHIFT 10 59*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_SYNCSRC_MASK BIT(FSL_AUDMIX_CTR_SYNCSRC_SHIFT) 60*4882a593Smuzhiyun #define FSL_AUDMIX_CTR_SYNCSRC(i) ((i) << FSL_AUDMIX_CTR_SYNCSRC_SHIFT) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* AUDMIX Status Register */ 63*4882a593Smuzhiyun #define FSL_AUDMIX_STR_RATEDIFF BIT(0) 64*4882a593Smuzhiyun #define FSL_AUDMIX_STR_CLKDIFF BIT(1) 65*4882a593Smuzhiyun #define FSL_AUDMIX_STR_MIXSTAT_SHIFT 2 66*4882a593Smuzhiyun #define FSL_AUDMIX_STR_MIXSTAT_MASK (0x3 << FSL_AUDMIX_STR_MIXSTAT_SHIFT) 67*4882a593Smuzhiyun #define FSL_AUDMIX_STR_MIXSTAT(i) (((i) & FSL_AUDMIX_STR_MIXSTAT_MASK) \ 68*4882a593Smuzhiyun >> FSL_AUDMIX_STR_MIXSTAT_SHIFT) 69*4882a593Smuzhiyun /* AUDMIX Attenuation Control Register */ 70*4882a593Smuzhiyun #define FSL_AUDMIX_ATCR_AT_EN BIT(0) 71*4882a593Smuzhiyun #define FSL_AUDMIX_ATCR_AT_UPDN BIT(1) 72*4882a593Smuzhiyun #define FSL_AUDMIX_ATCR_ATSTPDIF_SHIFT 2 73*4882a593Smuzhiyun #define FSL_AUDMIX_ATCR_ATSTPDFI_MASK \ 74*4882a593Smuzhiyun (0xfff << FSL_AUDMIX_ATCR_ATSTPDIF_SHIFT) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* AUDMIX Attenuation Initial Value Register */ 77*4882a593Smuzhiyun #define FSL_AUDMIX_ATIVAL_ATINVAL_MASK 0x3FFFF 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* AUDMIX Attenuation Step Up Factor Register */ 80*4882a593Smuzhiyun #define FSL_AUDMIX_ATSTPUP_ATSTEPUP_MASK 0x3FFFF 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* AUDMIX Attenuation Step Down Factor Register */ 83*4882a593Smuzhiyun #define FSL_AUDMIX_ATSTPDN_ATSTEPDN_MASK 0x3FFFF 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* AUDMIX Attenuation Step Target Register */ 86*4882a593Smuzhiyun #define FSL_AUDMIX_ATSTPTGT_ATSTPTG_MASK 0x3FFFF 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* AUDMIX Attenuation Value Register */ 89*4882a593Smuzhiyun #define FSL_AUDMIX_ATTNVAL_ATCURVAL_MASK 0x3FFFF 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* AUDMIX Attenuation Step Number Register */ 92*4882a593Smuzhiyun #define FSL_AUDMIX_ATSTP_STPCTR_MASK 0x3FFFF 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define FSL_AUDMIX_MAX_DAIS 2 95*4882a593Smuzhiyun struct fsl_audmix { 96*4882a593Smuzhiyun struct platform_device *pdev; 97*4882a593Smuzhiyun struct regmap *regmap; 98*4882a593Smuzhiyun struct clk *ipg_clk; 99*4882a593Smuzhiyun spinlock_t lock; /* Protect tdms */ 100*4882a593Smuzhiyun u8 tdms; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #endif /* __FSL_AUDMIX_H */ 104