Searched refs:TSP_SECBUF_OWNER_MASK (Results 1 – 13 of 13) sorted by relevance
404 #define TSP_SECBUF_OWNER_MASK 0x60000000 macro
307 #define TSP_SECBUF_OWNER_MASK 0x60000000 macro
2496 reg = TSP32_IdrR(&pSecBuf->Start) & (TSP_SECBUF_OWNER_MASK | TSP_SECBUF_ALLOC_MASK); in HAL_TSP_SecBuf_TryAlloc()2502 reg |= TSP_SECBUF_ALLOC_MASK | ((u16TSPId<<TSP_SECBUF_OWNER_SHFT) & TSP_SECBUF_OWNER_MASK); in HAL_TSP_SecBuf_TryAlloc()
342 #define TSP_SECBUF_OWNER_MASK 0x60000000 macro
3396 reg = TSP32_IdrR(&pSecBuf->Start) & (TSP_SECBUF_OWNER_MASK | TSP_SECBUF_ALLOC_MASK); in HAL_TSP_SecBuf_TryAlloc()3402 reg |= TSP_SECBUF_ALLOC_MASK | ((u16TSPId<<TSP_SECBUF_OWNER_SHFT) & TSP_SECBUF_OWNER_MASK); in HAL_TSP_SecBuf_TryAlloc()
344 #define TSP_SECBUF_OWNER_MASK 0x60000000 macro
376 #define TSP_SECBUF_OWNER_MASK 0x60000000 macro
377 #define TSP_SECBUF_OWNER_MASK 0x60000000 macro
3609 reg = TSP32_IdrR(&pSecBuf->Start) & (TSP_SECBUF_OWNER_MASK | TSP_SECBUF_ALLOC_MASK); in HAL_TSP_SecBuf_TryAlloc()3615 reg |= TSP_SECBUF_ALLOC_MASK | ((u16TSPId<<TSP_SECBUF_OWNER_SHFT) & TSP_SECBUF_OWNER_MASK); in HAL_TSP_SecBuf_TryAlloc()
3461 reg = TSP32_IdrR(&pSecBuf->Start) & (TSP_SECBUF_OWNER_MASK | TSP_SECBUF_ALLOC_MASK); in HAL_TSP_SecBuf_TryAlloc()3467 reg |= TSP_SECBUF_ALLOC_MASK | ((u16TSPId<<TSP_SECBUF_OWNER_SHFT) & TSP_SECBUF_OWNER_MASK); in HAL_TSP_SecBuf_TryAlloc()