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Searched refs:TSP_PS_VID_3D_EN (Results 1 – 13 of 13) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h958 …#define TSP_PS_VID_3D_EN 0x2000 //Set 1 to enable video 3D pat… macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DhalTSP.c2922 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_ClearAll()
3044 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
3064 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
H A DregTSP.h872 …#define TSP_PS_VID_3D_EN 0x2000 //Set 1 to enable video 3D pat… macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DregTSP.h908 …#define TSP_PS_VID_3D_EN 0x2000 //Set 1 to enable video 3D pat… macro
H A DhalTSP.c3838 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_ClearAll()
3978 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
4004 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h910 …#define TSP_PS_VID_3D_EN 0x2000 //Set 1 to enable video 3D pat… macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h948 …#define TSP_PS_VID_3D_EN 0x2000 //Set 1 to enable video 3D pat… macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h935 …#define TSP_PS_VID_3D_EN 0x2000 //Set 1 to enable video 3D pat… macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h935 …#define TSP_PS_VID_3D_EN 0x2000 //Set 1 to enable video 3D pat… macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h950 …#define TSP_PS_VID_3D_EN 0x2000 //Set 1 to enable video 3D pat… macro
H A DhalTSP.c4239 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_ClearAll()
4391 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
4423 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DhalTSP.c4007 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_ClearAll()
4142 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
4168 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
H A DregTSP.h935 …#define TSP_PS_VID_3D_EN 0x2000 //Set 1 to enable video 3D pat… macro