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Searched refs:SC1_REG_BASE (Results 1 – 25 of 47) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h127 #define SC1_REG_BASE BK_SCALER_BASE macro
163 u8Bank = msReadByte(SC1_REG_BASE); \
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
166 #define msDBC_FunctionExit() msWriteByte(SC1_REG_BASE, u8Bank)// for register bank s…
/utopia/UTPA2-700.0.x/modules/dlc/hal/mainz/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h127 #define SC1_REG_BASE BK_SCALER_BASE macro
163 u8Bank = msReadByte(SC1_REG_BASE); \
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
166 #define msDBC_FunctionExit() msWriteByte(SC1_REG_BASE, u8Bank)// for register bank s…
/utopia/UTPA2-700.0.x/modules/dlc/hal/maxim/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h127 #define SC1_REG_BASE BK_SCALER_BASE macro
163 u8Bank = msReadByte(SC1_REG_BASE); \
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
166 #define msDBC_FunctionExit() msWriteByte(SC1_REG_BASE, u8Bank)// for register bank s…
/utopia/UTPA2-700.0.x/modules/dlc/hal/maserati/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h127 #define SC1_REG_BASE BK_SCALER_BASE macro
163 u8Bank = msReadByte(SC1_REG_BASE); \
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
166 #define msDBC_FunctionExit() msWriteByte(SC1_REG_BASE, u8Bank)// for register bank s…
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h127 #define SC1_REG_BASE BK_SCALER_BASE macro
163 u8Bank = msReadByte(SC1_REG_BASE); \
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
166 #define msDBC_FunctionExit() msWriteByte(SC1_REG_BASE, u8Bank)// for register bank s…
/utopia/UTPA2-700.0.x/modules/dlc/hal/mustang/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h127 #define SC1_REG_BASE BK_SCALER_BASE macro
163 u8Bank = msReadByte(SC1_REG_BASE); \
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
166 #define msDBC_FunctionExit() msWriteByte(SC1_REG_BASE, u8Bank)// for register bank s…
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7621/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h127 #define SC1_REG_BASE BK_SCALER_BASE macro
163 u8Bank = msReadByte(SC1_REG_BASE); \
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
166 #define msDBC_FunctionExit() msWriteByte(SC1_REG_BASE, u8Bank)// for register bank s…
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7821/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h127 #define SC1_REG_BASE BK_SCALER_BASE macro
163 u8Bank = msReadByte(SC1_REG_BASE); \
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
166 #define msDBC_FunctionExit() msWriteByte(SC1_REG_BASE, u8Bank)// for register bank s…
/utopia/UTPA2-700.0.x/modules/dlc/hal/mooney/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h127 #define SC1_REG_BASE BK_SCALER_BASE macro
163 u8Bank = msReadByte(SC1_REG_BASE); \
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
166 #define msDBC_FunctionExit() msWriteByte(SC1_REG_BASE, u8Bank)// for register bank s…
/utopia/UTPA2-700.0.x/modules/dlc/hal/kano/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h127 #define SC1_REG_BASE BK_SCALER_BASE macro
163 u8Bank = msReadByte(SC1_REG_BASE); \
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
166 #define msDBC_FunctionExit() msWriteByte(SC1_REG_BASE, u8Bank)// for register bank s…
/utopia/UTPA2-700.0.x/modules/dlc/hal/maldives/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h127 #define SC1_REG_BASE BK_SCALER_BASE macro
163 u8Bank = msReadByte(SC1_REG_BASE); \
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
166 #define msDBC_FunctionExit() msWriteByte(SC1_REG_BASE, u8Bank)// for register bank s…
/utopia/UTPA2-700.0.x/modules/dlc/hal/macan/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h127 #define SC1_REG_BASE BK_SCALER_BASE macro
163 u8Bank = msReadByte(SC1_REG_BASE); \
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
166 #define msDBC_FunctionExit() msWriteByte(SC1_REG_BASE, u8Bank)// for register bank s…
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6lite/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h127 #define SC1_REG_BASE BK_SCALER_BASE macro
163 u8Bank = msReadByte(SC1_REG_BASE); \
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
166 #define msDBC_FunctionExit() msWriteByte(SC1_REG_BASE, u8Bank)// for register bank s…
/utopia/UTPA2-700.0.x/modules/dlc/hal/messi/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h127 #define SC1_REG_BASE BK_SCALER_BASE macro
163 u8Bank = msReadByte(SC1_REG_BASE); \
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
166 #define msDBC_FunctionExit() msWriteByte(SC1_REG_BASE, u8Bank)// for register bank s…
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h127 #define SC1_REG_BASE BK_SCALER_BASE macro
163 u8Bank = msReadByte(SC1_REG_BASE); \
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
166 #define msDBC_FunctionExit() msWriteByte(SC1_REG_BASE, u8Bank)// for register bank s…
/utopia/UTPA2-700.0.x/modules/graphic/hal/messi/gop/
H A DhalGOP.c619 case SC1_REG_BASE: in HAL_GOP_Read16Reg()
631 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Read16Reg()
710 case SC1_REG_BASE: in HAL_GOP_Write16Reg()
721 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Write16Reg()
782 case SC1_REG_BASE: in HAL_GOP_Write32Reg()
2100 case SC1_REG_BASE: in HAL_GOP_CMDQ_WriteCommand()
/utopia/UTPA2-700.0.x/modules/graphic/hal/mainz/gop/
H A DhalGOP.c619 case SC1_REG_BASE: in HAL_GOP_Read16Reg()
631 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Read16Reg()
710 case SC1_REG_BASE: in HAL_GOP_Write16Reg()
721 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Write16Reg()
782 case SC1_REG_BASE: in HAL_GOP_Write32Reg()
2100 case SC1_REG_BASE: in HAL_GOP_CMDQ_WriteCommand()
/utopia/UTPA2-700.0.x/modules/graphic/hal/maldives/gop/
H A DhalGOP.c499 case SC1_REG_BASE: in HAL_GOP_Read16Reg()
511 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Read16Reg()
566 case SC1_REG_BASE: in HAL_GOP_Write16Reg()
577 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Write16Reg()
625 case SC1_REG_BASE: in HAL_GOP_Write32Reg()
/utopia/UTPA2-700.0.x/modules/graphic/hal/mustang/gop/
H A DhalGOP.c502 case SC1_REG_BASE: in HAL_GOP_Read16Reg()
514 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Read16Reg()
569 case SC1_REG_BASE: in HAL_GOP_Write16Reg()
580 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Write16Reg()
628 case SC1_REG_BASE: in HAL_GOP_Write32Reg()
/utopia/UTPA2-700.0.x/modules/graphic/hal/mooney/gop/
H A DhalGOP.c611 case SC1_REG_BASE: in HAL_GOP_Read16Reg()
623 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Read16Reg()
702 case SC1_REG_BASE: in HAL_GOP_Write16Reg()
713 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Write16Reg()
782 case SC1_REG_BASE: in HAL_GOP_Write32Reg()
2439 case SC1_REG_BASE: in HAL_GOP_CMDQ_WriteCommand()
/utopia/UTPA2-700.0.x/modules/graphic/hal/manhattan/gop/
H A DhalGOP.c657 case SC1_REG_BASE: in HAL_GOP_Read16Reg()
669 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Read16Reg()
748 case SC1_REG_BASE: in HAL_GOP_Write16Reg()
759 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Write16Reg()
828 case SC1_REG_BASE: in HAL_GOP_Write32Reg()
2861 case SC1_REG_BASE:
/utopia/UTPA2-700.0.x/modules/graphic/hal/macan/gop/
H A DhalGOP.c688 case SC1_REG_BASE: in HAL_GOP_Read16Reg()
700 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Read16Reg()
779 case SC1_REG_BASE: in HAL_GOP_Write16Reg()
790 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Write16Reg()
859 case SC1_REG_BASE: in HAL_GOP_Write32Reg()
2989 case SC1_REG_BASE: in HAL_GOP_CMDQ_WriteCommand()
/utopia/UTPA2-700.0.x/modules/graphic/hal/kastor/gop/
H A DhalGOP.c730 case SC1_REG_BASE: in HAL_GOP_Read16Reg()
742 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Read16Reg()
822 case SC1_REG_BASE: in HAL_GOP_Write16Reg()
833 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Write16Reg()
904 case SC1_REG_BASE: in HAL_GOP_Write32Reg()
3205 case SC1_REG_BASE: in HAL_GOP_CMDQ_WriteCommand()
/utopia/UTPA2-700.0.x/modules/graphic/hal/curry/gop/
H A DhalGOP.c742 case SC1_REG_BASE: in HAL_GOP_Read16Reg()
754 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Read16Reg()
834 case SC1_REG_BASE: in HAL_GOP_Write16Reg()
845 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Write16Reg()
916 case SC1_REG_BASE: in HAL_GOP_Write32Reg()
3441 case SC1_REG_BASE: in HAL_GOP_CMDQ_WriteCommand()
/utopia/UTPA2-700.0.x/modules/graphic/hal/kano/gop/
H A DhalGOP.c733 case SC1_REG_BASE: in HAL_GOP_Read16Reg()
745 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Read16Reg()
825 case SC1_REG_BASE: in HAL_GOP_Write16Reg()
836 u32addr = SC1_REG_BASE + (u32addr & 0xFF); in HAL_GOP_Write16Reg()
907 case SC1_REG_BASE: in HAL_GOP_Write32Reg()
3516 case SC1_REG_BASE: in HAL_GOP_CMDQ_WriteCommand()

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