1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MsCommon.h"
96 #ifndef MSOS_TYPE_LINUX_KERNEL
97 #include <string.h>
98 #endif
99 #include "MsTypes.h"
100 #include "halGOP.h"
101 #include "regGOP.h"
102 #include "halCHIP.h"
103 #include "drvSYS.h"
104
105 //------------------------------------------------------------------------------
106 // Driver Compiler Options
107 //------------------------------------------------------------------------------
108 #define HAL_GOP_DEBUGINFO(x) //x
109
110 //------------------------------------------------------------------------------
111 // Local Defines
112 //------------------------------------------------------------------------------
113 #define RIU ((unsigned short volatile *) pGOPHalLocal->va_mmio_base)
114 #define GOP_WRITE2BYTE(addr, val) { RIU[addr] = val; }
115 #define GOP_READ2BYTE(addr) RIU[addr]
116 #define GOP_DST_MASK 0x7UL
117
118 //------------------------------------------------------------------------------
119 // Local Var
120 //------------------------------------------------------------------------------
121 MS_BOOL bIsMuxVaildToGopDst[MAX_GOP_MUX][MAX_DRV_GOP_DST_SUPPORT] =
122 {
123 /*IP0, IP0_SUB, MIXER2VE, OP0, VOP, IP1, IP1_SUB, MIXER2OP*/
124 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
125 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 1 */
126 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
127 };
128 #ifdef GOP_CMDQ_ENABLE
129 extern MS_U16 u16MIUSelect[MAX_GOP_SUPPORT];
130 extern MS_U8 bMIUSelect[MAX_GOP_SUPPORT];
131 #endif
132 GOP_CHIP_PROPERTY g_GopChipPro =
133 {
134 .bSetHSyncInverse = TRUE,
135 .bGop1GPalette = FALSE,
136 .bSetHPipeOfst = FALSE,
137 .bNeedCheckMVOP = FALSE,
138 .bNeedSetMUX1ToIP0 = TRUE,
139 .bNeedSetMUX3ToIP0 = FALSE,
140 .bNewMux = FALSE,
141 .bNewPalette = TRUE,
142 .bNewBwReg = TRUE,
143 .bGop2VStretch = TRUE,
144 .bIgnoreIPHPD = FALSE, //Uranus4 has handshack with XC, should not set HPD
145 .bIgnoreVEHPD = FALSE, //Uranus4 to VE through Mixer, do not need adjust HPD
146 .bhastilemode = FALSE,
147 .bInitNotEnableGOPToSC = FALSE, //For Uranus4 mux init setting, enable GOP to SC in GOP init would cause problem
148 .bAutoAdjustMirrorHSize = TRUE, //whether hw will auto adjust start addr when H mirror is enable
149 .bGOPWithVscale = {TRUE, TRUE, FALSE, FALSE}, //setting GOP with/without Vscale
150 .bGOPWithScaleDown = {FALSE, FALSE, FALSE, FALSE, FALSE},
151
152 .bDWINSupport = TRUE,
153 .DwinVer = 0x1,
154 .bTstPatternAlpha = TRUE,
155 .bXCDirrectBankSupport = TRUE, /*XC Dirrect Bank R/W*/
156 .bFRCSupport = FALSE, /*OC path*/
157 .bGOPMixerToVE= FALSE, /*Mixer to VE path*/
158 .bBnkForceWrite = FALSE, /*Direct Bank Force Write*/
159 .bPixelModeSupport = FALSE, /*Pixel Mode Support*/
160 .bScalingDownSupport= FALSE,
161 .b2Pto1PSupport= FALSE,
162 .bTLBSupport= {FALSE, FALSE, FALSE, FALSE, FALSE, FALSE},
163 .GOP_TestPattern_Vaild= E_GOP0,
164 .bInternalMIUSelect= {FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE}, //{E_GOP0, E_GOP1, E_GOP2, E_GOP3, E_GOP4, E_GOP_Dwin, E_GOP_MIXER, E_GOP5}
165
166 #ifdef ENABLE_GOP_T3DPATCH
167 .GOP_PD = 0xBF,
168 #else
169 .GOP_PD = 0x3F,
170 #endif
171 .GOP_UHD_PD_Offset = 0x0,
172 .GOP_IP_PD = (-0xC),
173 .GOP_MVOP_PD = 0x69,
174 .GOP_VE_PD = 0x89,
175 .GOP_MIXER_PD = 0x0,
176 .GOP_NonVS_PD_Offset = 0x5, //GOP without Vsacle might need add offset on pipedelay
177 .GOP_VE_V_Offset = 0x0,
178
179 .GOP_MUX_Delta = 0x1,
180 .GOP_Mux_Offset = {0x0, 0x2, 0x4, 0xF, 0x12},
181 .GOP_MapLayer2Mux = {E_GOP_MUX0, E_GOP_MUX1, E_GOP_MUX2, E_GOP_MUX3, E_GOP_MUX4},
182 .GOP_Mux_FRC_offset= 0x13,
183
184 .WordUnit = GOP_WordUnit,
185 .TotalGwinNum = GOP_TotalGwinNum,
186 .Default_ConsAlpha_bits = DRV_VALID_8BITS,
187 .enGOP3DType = E_DRV_3D_DUP_HALF,
188 };
189
190 //------------------------------------------------------------------------------
191 // Global Functions
192 //------------------------------------------------------------------------------
HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_TYPE_DEF * GOP_TYPE)193 void HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_TYPE_DEF* GOP_TYPE)
194 {
195 GOP_TYPE->GOP0 = E_GOP0;
196 GOP_TYPE->GOP1 = E_GOP1;
197 GOP_TYPE->GOP2 = E_GOP2;
198 GOP_TYPE->GOP3 = E_GOP3;
199 GOP_TYPE->GOP4 = E_GOP4;
200 GOP_TYPE->GOP5 = E_GOP5;
201 GOP_TYPE->DWIN = E_GOP_Dwin;
202 GOP_TYPE->MIXER = E_GOP_MIXER;
203 }
204
HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 regForm,MS_U8 u8GOPNum,MS_U8 u8GwinNum,MS_U16 colortype)205 GOP_Result HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 regForm, MS_U8 u8GOPNum, MS_U8 u8GwinNum, MS_U16 colortype)
206 {
207 MS_U32 u32BankOffSet = 0;
208
209 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
210
211 if (((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T21G) || ((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T81G))
212 {
213 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(Gop23_GwinCtl_Ofet), colortype, 0x00f0);
214 }
215 else
216 {
217 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(u8GwinNum), colortype, 0x00f0);
218 }
219
220 return GOP_SUCCESS;
221 }
222
HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn,E_DRV_GOP_PINPON_MODE pinpon_mode)223 GOP_Result HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum, MS_BOOL bEn, E_DRV_GOP_PINPON_MODE pinpon_mode)
224 {
225 MS_U32 u32BankOffSet =0;
226 MS_U32 u32BitMask,Regval;
227
228 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
229
230 switch(pinpon_mode)
231 {
232 default:
233 case E_DRV_GOP_PINPON_DWIN:
234 Regval = bEn << 7;
235 u32BitMask = GOP_BIT7;
236 break;
237 }
238
239 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, Regval, u32BitMask);
240 return GOP_SUCCESS;
241 }
242
243
_GetBnkOfstByGop(MS_U8 gop,MS_U32 * pBnkOfst)244 MS_BOOL _GetBnkOfstByGop(MS_U8 gop, MS_U32 *pBnkOfst)
245 {
246 if((gop >= MAX_GOP_SUPPORT)&&(gop != E_GOP_Dwin))
247 {
248 GOP_H_ERR("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
249 return FALSE;
250 }
251
252 if (gop==E_GOP0)
253 *pBnkOfst = GOP_4G_OFST<<16;
254 else if (gop==E_GOP1)
255 *pBnkOfst = GOP_2G_OFST<<16;
256 else if (gop==E_GOP2)
257 *pBnkOfst = GOP_1G_OFST<<16;
258 else if (gop==E_GOP_Dwin)
259 *pBnkOfst = GOP_DW_OFST<<16;
260 else
261 return FALSE;
262
263 return TRUE;
264 }
265
HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)266 GOP_Result HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
267 {
268 #ifdef GOP_BK_DOUBLE_BUF_WRITE
269 MS_U16 u16Bank = 0;
270 MS_U16 u16GetBank = 0;
271
272 u16GetBank = GOP_READ2BYTE(GOP_BAK_SEL)&0xF;
273
274 if (u16GopMask&GOP_BIT0)
275 {
276 u16Bank |= GOP_4G_OFST;
277 }
278 if (u16GopMask&GOP_BIT1)
279 {
280 u16Bank |= GOP_2G_OFST;
281 }
282 if (u16GopMask&GOP_BIT2)
283 {
284 u16Bank |= GOP_1G_OFST;
285 }
286 if (u16GopMask != 0)
287 {
288 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, u16Bank|GOP_BIT10 , GOP_BIT10|BMASK(3:0));
289 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, u16Bank , GOP_BIT10|BMASK(3:0));
290 }
291 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, u16GetBank , BMASK(3:0));
292 #else
293 MS_U16 u16Mask0 = 0;
294
295 if (u16GopMask&GOP_BIT0)
296 {
297 u16Mask0 |= GOP_BIT12;
298 }
299 if (u16GopMask&GOP_BIT1)
300 {
301 u16Mask0 |= GOP_BIT13;
302 }
303 if (u16GopMask&GOP_BIT2)
304 {
305 u16Mask0 |= GOP_BIT14;
306 }
307 if (u16Mask0 != 0)
308 {
309 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, 0xFFFF , u16Mask0);
310 }
311 #endif
312 return GOP_SUCCESS;
313 }
314
HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)315 GOP_Result HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
316 {
317 if((gop >= MAX_GOP_SUPPORT)&&(gop != E_GOP_Dwin))
318 {
319 GOP_H_ERR("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
320 return GOP_FAIL;
321 }
322 #ifdef GOP_BK_DOUBLE_BUF_WRITE
323 MS_U16 u16Bank = 0;
324 MS_U16 u16GetBank = 0;
325 u16GetBank = GOP_READ2BYTE(GOP_BAK_SEL)&0xF;
326
327 switch(gop)
328 {
329 case E_GOP0:
330 u16Bank |= GOP_4G_OFST;
331 break;
332 case E_GOP1:
333 u16Bank |= GOP_2G_OFST;
334 break;
335 case E_GOP2:
336 u16Bank |= GOP_1G_OFST;
337 break;
338 case E_GOP_Dwin:
339 u16Bank |= GOP_DW_OFST;
340 break;
341 default:
342 break;
343 }
344 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, u16Bank|GOP_BIT10 , GOP_BIT10|BMASK(3:0));
345 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, u16Bank , GOP_BIT10|BMASK(3:0));
346
347 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, u16GetBank , BMASK(3:0));
348 #else
349 switch(gop)
350 {
351 case E_GOP0:
352 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT12 , GOP_BIT12);
353 break;
354 case E_GOP1:
355 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT13 , GOP_BIT13);
356 break;
357 case E_GOP2:
358 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT14 , GOP_BIT14);
359 break;
360 case E_GOP_Dwin:
361 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, GOP_BIT13 , GOP_BIT13);
362 break;
363 default:
364 break;
365 }
366 #endif
367 return GOP_SUCCESS;
368 }
369
HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)370 MS_U16 HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
371 {
372 MS_U16 u16GopAck = 0,reg_val =0;
373
374 if((gop >= MAX_GOP_SUPPORT)&&(gop != E_GOP_Dwin))
375 {
376 GOP_H_ERR("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
377 return FALSE;
378 }
379
380 switch(gop)
381 {
382 case E_GOP0:
383 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
384 if(reg_val&GOP_BIT12)
385 u16GopAck = FALSE;
386 else
387 u16GopAck = TRUE;
388 break;
389 case E_GOP1:
390 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
391 if(reg_val&GOP_BIT13)
392 u16GopAck = FALSE;
393 else
394 u16GopAck = TRUE;
395 break;
396 case E_GOP2:
397 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
398 if(reg_val&GOP_BIT14)
399 u16GopAck = FALSE;
400 else
401 u16GopAck = TRUE;
402 break;
403 case E_GOP_Dwin:
404 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_MUX,®_val);
405 if(reg_val&GOP_BIT13)
406 u16GopAck = FALSE;
407 else
408 u16GopAck = TRUE;
409 break;
410 default:
411 break;
412 }
413 return u16GopAck;
414 }
415
HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)416 GOP_Result HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable)
417 {
418 return GOP_FUN_NOT_SUPPORTED;
419 }
420
HAL_GOP_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)421 void HAL_GOP_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
422 {
423 MS_U32 u32bankoff = 0;
424 MS_U16 mask_shift=0xFF;
425 MS_U16 u16RegVal=0xFF;
426 MS_U8 u8MIUSel=0xF;
427
428 if(u8GOPNum >= MAX_GOP_SUPPORT)
429 {
430 GOP_H_ERR("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8GOPNum);
431 return;
432 }
433
434 _GetBnkOfstByGop(u8GOPNum, &u32bankoff);
435 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_CTRL0, 0x000, GOP_BIT9); // Genshot fast=0 for t3, for T4 and after no need to set this bit.
436
437 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, 0xDFD0, GOP_REG_WORD_MASK); //set GOP DMA Burst length to "32", set DMA FIFO threhold to "0xD0"
438
439 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT14, GOP_BIT14);
440 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT12, GOP_BIT13|GOP_BIT12);
441
442 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_HW_USAGE, 0, GOP_BIT0);
443
444 /* enable GOP clock */
445 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, 0, CKG_SRAM0_DISABLE_CLK); /* GOP palette SRAM0&1 */
446 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, CKG_GOPD_DISABLE_CLK_MASK); /* GOP Line buffer sram clock */
447
448 switch(u8GOPNum)
449 {
450 case E_GOP0:
451 mask_shift = GOP_MIU_CLIENT_GOP0;
452 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG0_DISABLE_CLK_MASK); /* GOP 0 */
453 break;
454 case E_GOP1:
455 mask_shift = GOP_MIU_CLIENT_GOP1;
456 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG1_DISABLE_CLK_MASK); /* GOP 1 */
457 break;
458 case E_GOP2:
459 mask_shift = GOP_MIU_CLIENT_GOP2;
460 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, CKG_GOPG2_DISABLE_CLK_MASK); /* GOP 2 */
461 break;
462 default:
463 mask_shift = 0xFF;
464 return;
465 }
466
467
468 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOPNum] ==TRUE)
469 {
470 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal);
471 u8MIUSel = (u16RegVal>>mask_shift)&0x0000001UL;
472 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel, GOP_BIT0|GOP_BIT1 );//GWIN MIU Select
473 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP, 1<<mask_shift, 1<<mask_shift );//Get Control MIU select by GOP itself
474 }
475
476 }
477
HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal)478 void HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
479 {
480 *pGOPHalLocal->pGopChipPro = g_GopChipPro;
481 }
482
HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)483 MS_U8 HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
484 {
485 switch(u8GopNum)
486 {
487 case E_GOP0:
488 return (MS_U8)MAX_GOP0_GWIN;
489 break;
490 case E_GOP1:
491 return (MS_U8)MAX_GOP1_GWIN;
492 break;
493 case E_GOP2:
494 return (MS_U8)MAX_GOP2_GWIN;
495 break;
496 default:
497 MS_ASSERT(0);
498 return 0xFF;
499 break;
500 }
501 }
502
HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8Gop,MS_U8 u8Idx)503 MS_U8 HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8Gop, MS_U8 u8Idx)
504 {
505 MS_U8 u8GWinId = 0;
506
507 //Adjust GWIN ID by different Chip
508 if(u8Gop >= MAX_GOP_SUPPORT)
509 {
510 GOP_H_FATAL("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8Gop);
511 MS_ASSERT(0);
512 return 0xFF;
513 }
514
515 switch(u8Gop)
516 {
517 case E_GOP0:
518 u8GWinId = GOP0_GwinIdBase + u8Idx;
519 break;
520 case E_GOP1:
521 u8GWinId = GOP1_GwinIdBase + u8Idx;
522 break;
523 case E_GOP2:
524 u8GWinId = GOP2_GwinIdBase + u8Idx;
525 break;
526 default:
527 break;
528 }
529 return u8GWinId;
530
531 }
532
HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)533 GOP_Result HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
534 {
535 if(u8GOPNum >= MAX_GOP_SUPPORT)
536 {
537 GOP_H_FATAL("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8GOPNum);
538 MS_ASSERT(0);
539 return 0xFF;
540 }
541
542 switch(u8GOPNum)
543 {
544 case E_GOP0: // GOP4G
545 pGOPHalLocal->bank_offset = GOP_4G_OFST<<16;
546 return GOP_SUCCESS;
547 case E_GOP1: // GOP2G
548 pGOPHalLocal->bank_offset = GOP_2G_OFST<<16;
549 return GOP_SUCCESS;
550 case E_GOP2: // GOP1G
551 pGOPHalLocal->bank_offset = GOP_1G_OFST<<16;
552 return GOP_SUCCESS;
553 case E_GOP_Dwin: // GOPDWX
554 pGOPHalLocal->bank_offset = GOP_DW_OFST<<16;
555 return GOP_SUCCESS;
556 default:
557 MS_ASSERT(0);
558 return GOP_FAIL;
559 }
560 }
561
HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8bank)562 void HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8bank)
563 {
564 MS_U16 u16Bank;
565 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL);
566 u16Bank &= ~BMASK(3:0);
567 u16Bank |= (u8bank&BMASK(3:0));
568 GOP_WRITE2BYTE(GOP_BAK_SEL, u16Bank);
569 }
570
HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL * pGOPHalLocal)571 MS_U8 HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
572 {
573 MS_U16 u16GetBank;
574 u16GetBank = GOP_READ2BYTE(GOP_BAK_SEL)&0xF;
575 return u16GetBank;
576 }
577
HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 * pu16ret)578 void HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16* pu16ret)
579 {
580 MS_U16 u16xcSubbank=0, u16BankAddr=0, u16BankTemp=0;
581 MS_U32 bank;
582 MS_U32 direct_addr;
583
584 HAL_GOP_DEBUGINFO(GOP_H_INFO("HAL_GOP_Read16Reg[%x]\n", u32addr));
585
586 //* Gop driver should access another HW IP register
587 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
588 switch (u32addr & 0xFF00)
589 {
590 case GOP_REG_BASE:
591 {
592 bank = (u32addr & 0xFF0000) >> 8;
593
594 if(bank==0xE00)//GOP4: 0x121B00
595 {
596 bank=GOP_REG_GOP4_BK_OFFSET;
597 }
598 else if(bank==0xF00)//GWIN4: 0x121E00
599 {
600 bank=GOP_REG_GOP4_GW_OFFSET;
601 }
602 else if(bank==0x1000)//GOP4_ST
603 {
604 bank=GOP_REG_GOP4_ST_OFFSET;
605 }
606 #ifdef GOP_VSTRETCH_OLD_MODE
607 if( (bank==0x600) && ((u32addr&0xFF)==(GOP_4G_STRCH_VSZ&0xFF)) ) //GOP2: 0x120800
608 {
609 *pu16ret = pGOPHalLocal->pHALShared->u16GOPSrcHeight[E_GOP2];
610 }
611 else
612 #endif
613 {
614 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF); //Direct_Base + bank + addr_offset
615 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
616 }
617 break;
618 }
619 case SC1_REG_BASE:
620 {
621 if(g_GopChipPro.bXCDirrectBankSupport)
622 {
623 u16xcSubbank = (u32addr & 0xFF0000)>>8;
624 u32addr = SC1_DIRREG_BASE+ u16xcSubbank + (u32addr & 0xFF);
625 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFFF));
626 }
627 else
628 {
629 u16xcSubbank = (u32addr & 0xFF0000)>>16;
630 u16BankAddr = GOP_SC_BANKSEL+0;
631 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
632
633 u16BankTemp = GOP_READ2BYTE(u16BankAddr&0xFFFF);
634 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16xcSubbank);
635 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
636 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16BankTemp);
637 }
638 break;
639 }
640 case GE_REG_BASE:
641 case CKG_REG_BASE:
642 case MIU0_REG_BASE:
643 case MIU_REG_BASE:
644 case MVOP_REG_BASE:
645 {
646 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
647 break;
648 }
649
650 default:
651 {
652 //Gop lib current do not support this HW ip base
653 MS_ASSERT(0);
654 *pu16ret =0;
655 break;
656 }
657 }
658 }
659
HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)660 void HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
661 {
662 MS_U16 u16tmp=0;
663 MS_U16 u16xcSubbank=0,u16BankAddr=0,pu16ret=0;
664 MS_U32 bank;
665 MS_U32 direct_addr;
666
667 HAL_GOP_DEBUGINFO(GOP_H_INFO("HAL_GOP_Write16Reg[%04x] = %04x\n", u32addr, u16val));
668
669 if(mask!=0xffff)
670 {
671 HAL_GOP_Read16Reg(pGOPHalLocal, u32addr, &u16tmp);
672 u16tmp &= ~mask;
673 u16val &= mask;
674 u16val |= u16tmp;
675 }
676
677 //* Gop driver should access another HW IP register
678 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
679 switch (u32addr & 0xFF00)
680 {
681 case GOP_REG_BASE:
682 {
683 bank = (u32addr & 0xFF0000) >> 8;
684
685 if(bank==0xE00)//GOP4: 0x121B00
686 {
687 bank=GOP_REG_GOP4_BK_OFFSET;
688 }
689 else if(bank==0xF00)//GWIN4: 0x121E00
690 {
691 bank=GOP_REG_GOP4_GW_OFFSET;
692 }
693 else if(bank==0x1000) //GOP4_ST
694 {
695 bank=GOP_REG_GOP4_ST_OFFSET;
696 }
697
698 #ifdef GOP_VSTRETCH_OLD_MODE
699 if( (bank==0x600) && ((u32addr&0xFF)==(GOP_4G_STRCH_VSZ&0xFF)) ) //GOP2: 0x120800
700 {
701 pGOPHalLocal->pHALShared->u16GOPSrcHeight[E_GOP2] = u16val;
702 u16val = GOP_VSTRETCH_FULL_SIZE;
703 }
704 #endif
705
706 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
707 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
708 break;
709 }
710 case SC1_REG_BASE:
711 if(g_GopChipPro.bXCDirrectBankSupport)
712 { /*Derrick Bank*/
713 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
714 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
715 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
716 }
717 else
718 { /*Sub Bank*/
719 u16xcSubbank = (u32addr & 0xFF0000)>>16 ;
720 u16BankAddr = GOP_SC_BANKSEL+0;
721 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
722
723 pu16ret = GOP_READ2BYTE(u16BankAddr&0xFFFF);
724 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), u16xcSubbank);
725 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
726 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), pu16ret);
727 }
728 break;
729 case GE_REG_BASE:
730 case CKG_REG_BASE:
731 case MIU0_REG_BASE:
732 case MIU_REG_BASE:
733 {
734 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
735 break;
736 }
737 default:
738 {
739 //Gop lib current do not support this HW ip base
740 MS_ASSERT(0);
741 break;
742 }
743
744 }
745 }
746
747
HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U32 u32val)748 void HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U32 u32val)
749 {
750 MS_U32 bank;
751 MS_U32 direct_addr;
752
753 HAL_GOP_DEBUGINFO(GOP_H_INFO("HAL_GOP_Write32Reg[%bx] = %lx\n", u32addr, u32val));
754
755 //* Gop driver should access another HW IP register
756 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
757 switch (u32addr & 0xFF00)
758 {
759 case GOP_REG_BASE:
760 {
761 bank = (u32addr & 0xFF0000) >> 8;
762 if(bank==0xE00)//GOP4: 0x121B00
763 {
764 bank=GOP_REG_GOP4_BK_OFFSET;
765 }
766 else if(bank==0xF00)//GWIN4: 0x121E00
767 {
768 bank=GOP_REG_GOP4_GW_OFFSET;
769 }
770 else if(bank==0x1000) //GOP4_ST
771 {
772 bank=GOP_REG_GOP4_ST_OFFSET;
773 }
774
775 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
776 GOP_WRITE2BYTE((direct_addr&0xFFFFF), (u32val&0xFFFF));
777 GOP_WRITE2BYTE((direct_addr&0xFFFFF)+2, (u32val&0xFFFF0000)>>16);
778 break;
779 }
780
781 case GE_REG_BASE:
782 case SC1_REG_BASE:
783 case CKG_REG_BASE:
784 {
785 GOP_WRITE2BYTE((u32addr&0xFFFF), (u32val&0xFFFF));
786 GOP_WRITE2BYTE((u32addr&0xFFFF)+2, (u32val&0xFFFF0000)>>16);
787 break;
788 }
789
790 default:
791 {
792 //Gop lib current do not support this HW ip base
793 MS_ASSERT(0);
794 break;
795 }
796
797 }
798 }
799
800 //extern E_BDMA_Ret MDrv_BDMA_Mem_Fill(MS_U32 u32Addr, MS_U32 u32Len, MS_U32 u32Pattern, E_BDMA_DstDev eDev);
801
HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * pREGMAP_Base,MS_U16 * pREGMAP_Offset,MS_U32 u32REGMAP_Len,MS_U8 u8Index,MS_U8 u8A,MS_U8 u8R,MS_U8 u8G,MS_U8 u8B)802 void HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL *pGOPHalLocal,
803 MS_U8 *pREGMAP_Base, MS_U16 *pREGMAP_Offset, MS_U32 u32REGMAP_Len,
804 MS_U8 u8Index, MS_U8 u8A, MS_U8 u8R, MS_U8 u8G, MS_U8 u8B)
805 {
806 MS_U8 i=0;
807 HAL_GOP_DEBUGINFO(GOP_H_INFO("GOP_Write32Pal : i= %02bx, ARGB = %02bx,%02bx,%02bx,%02bx\n",u8Index, u8A, u8R, u8G, u8B));
808
809 /* Don't care high byte */
810 MS_ASSERT((MS_U32)(*pREGMAP_Offset +GOP_WordUnit)<= u32REGMAP_Len);
811
812 for(i =(GOP_WordUnit-1);i>4;i--)
813 {
814 *(pREGMAP_Base + *pREGMAP_Offset + i) = 0;
815 }
816 *(pREGMAP_Base + *pREGMAP_Offset + 4) = u8Index;
817 *(pREGMAP_Base + *pREGMAP_Offset + 3) = u8A;
818 *(pREGMAP_Base + *pREGMAP_Offset + 2) = u8R;
819 *(pREGMAP_Base + *pREGMAP_Offset + 1) = u8G;
820 *(pREGMAP_Base + *pREGMAP_Offset) = u8B;
821 *pREGMAP_Offset += GOP_WordUnit;
822
823 MsOS_FlushMemory(); //make sure cpu write data to dram
824
825 }
826
HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPColorType fbFmt)827 MS_U16 HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPColorType fbFmt)
828 {
829 MS_U16 bpp=0;
830
831 switch ( fbFmt )
832 {
833 case E_DRV_GOP_COLOR_RGB555_BLINK :
834 case E_DRV_GOP_COLOR_RGB565 :
835 case E_DRV_GOP_COLOR_ARGB1555:
836 case E_DRV_GOP_COLOR_RGBA5551:
837 case E_DRV_GOP_COLOR_ARGB4444 :
838 case E_DRV_GOP_COLOR_RGBA4444 :
839 case E_DRV_GOP_COLOR_RGB555YUV422:
840 case E_DRV_GOP_COLOR_YUV422:
841 case E_DRV_GOP_COLOR_2266:
842 bpp = 16;
843 break;
844 case E_DRV_GOP_COLOR_ARGB8888 :
845 case E_DRV_GOP_COLOR_ABGR8888 :
846 bpp = 32;
847 break;
848
849 case E_DRV_GOP_COLOR_I8 :
850 bpp = 8;
851 break;
852
853 default :
854 //print err
855 MS_ASSERT(0);
856 bpp = 0xFFFF;
857 break;
858 }
859 return bpp;
860
861 }
862
HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,MS_U8 u8coef)863 void HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, MS_U8 u8coef)
864 {
865 MS_U16 regval;
866 MS_U8 u8coef_cpt = u8coef;
867
868 if( pGOPHalLocal->User_ConsAlpha_bits != g_GopChipPro.Default_ConsAlpha_bits)
869 {
870 switch(u8coef)
871 {
872 case 0x0 :
873 u8coef_cpt = u8coef<<2;
874 break;
875 case 0x3f :
876 u8coef_cpt = ((u8coef<<2)|0x3);
877 break;
878 default:
879 u8coef_cpt = ((u8coef<<2)|0x1);
880 break;
881 }
882 }
883
884 if (u8win<(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
885 {
886 regval = (MS_U16)(bEnable?(1<<14):0);
887 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN0_CTRL(u8win):GOP_2G_GWIN_CTRL(u8win-MAX_GOP0_GWIN), regval, 0x4000);
888 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN_ALPHA01(u8win):GOP_2G_GWIN_ALPHA01(u8win-MAX_GOP0_GWIN), u8coef_cpt, 0xFF);
889 }
890 else
891 {
892 if (u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
893 {
894 regval = (MS_U16)(bEnable?(1<<14):0);
895 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN0_CTRL, regval, 0x4000);
896 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u8coef, 0xFF);
897 }
898 else
899 {
900 regval = (MS_U16)(bEnable?(1<<14):0);
901 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN0_CTRL, regval, 0x4000);
902 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u8coef, 0xFF);
903 }
904 }
905 }
906
HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)907 void HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
908 {
909 pGOPHalLocal->va_mmio_base = addr;
910 }
HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)911 void HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
912 {
913 }
HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)914 void HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
915 {
916 }
917
918
HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)919 GOP_Result HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)
920 {
921 /* GOP dst type:
922 1: IP (Main)
923 0: IP (Sub)
924 2: OP
925 */
926 MS_U16 u16RegVal;
927 MS_U32 u32BankOffSet;
928 MS_U16 u16HSyncMask=GOP_BIT14;
929
930 if( GopNum >= MAX_GOP_SUPPORT)
931 {
932 GOP_H_ERR("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,GopNum);
933 return GOP_INVALID_PARAMETERS;
934 }
935
936 switch (eDstType)
937 {
938 case E_DRV_GOP_DST_IP0:
939 u16RegVal = 0x0;
940 u16HSyncMask=GOP_BIT14;
941 break;
942
943 case E_DRV_GOP_DST_IP0_SUB:
944 u16RegVal = 0x1;
945 u16HSyncMask=GOP_BIT14;
946 break;
947
948 case E_DRV_GOP_DST_OP0:
949 u16RegVal = 0x2;
950 u16HSyncMask=GOP_BIT14;
951 break;
952
953 case E_DRV_GOP_DST_VOP:
954 u16RegVal = 0x3;
955 u16HSyncMask=GOP_BIT14;
956 break;
957
958 case E_DRV_GOP_DST_VOP_SUB:
959 u16RegVal = 0x4;
960 u16HSyncMask=GOP_BIT14;
961 break;
962
963 default:
964 return GOP_FUN_NOT_SUPPORTED;
965 }
966 if(bOnlyCheck == FALSE)
967 {
968 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
969 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(GOP_BIT3:0));
970
971 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, (MS_U16)~GOP_BIT1, GOP_BIT1);
972
973 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, u16HSyncMask, GOP_BIT14); // Set mask Hsync when VFDE is low
974 }
975 return GOP_SUCCESS;
976 }
977
HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType eDstType)978 GOP_Result HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType eDstType)
979 {
980 return GOP_FUN_NOT_SUPPORTED;
981 }
982
HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType * pGopDst)983 GOP_Result HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType *pGopDst)
984 {
985 return GOP_FUN_NOT_SUPPORTED;
986 }
987
HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal)988 GOP_Result HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
989 {
990 /*T8
991 OP path: support 3 mux (mux0, mux 2, mux3) to blend with SC simultaneously
992 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
993 SW default setting=> mux0:gop1g, mux1:gop1gx, mux2:gop2g, mux3:gop4g
994 */
995 MS_U8 gop4g=0, gop2g=1, gop1g=2;
996 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, ((gop1g<<(GOP_MUX_SHIFT*2))|(gop4g<<(GOP_MUX_SHIFT*1))|gop2g), GOP_REG_WORD_MASK);
997 return GOP_SUCCESS;
998 }
999
HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * u8GOPNum,Gop_MuxSel eGopMux)1000 void HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8* u8GOPNum, Gop_MuxSel eGopMux)
1001 {
1002 MS_U16 u16GopMux=0;
1003
1004 switch(eGopMux)
1005 {
1006 case E_GOP_MUX0:
1007 case E_GOP_MUX1:
1008 case E_GOP_MUX2:
1009 case E_GOP_IP0_MUX:
1010 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16GopMux);
1011 *u8GOPNum = (u16GopMux >> ((eGopMux%4)*GOP_MUX_SHIFT))& GOP_REGMUX_MASK;
1012 break;
1013 case E_GOP_MUX3:
1014 case E_GOP_MUX4:
1015 case E_GOP_IP1_MUX:
1016 case E_GOP_VOP0_MUX:
1017 case E_GOP_VOP1_MUX:
1018 case E_GOP_FRC_MUX0:
1019 case E_GOP_FRC_MUX1:
1020 case E_GOP_FRC_MUX2:
1021 case E_GOP_FRC_MUX3:
1022 case E_GOP_BYPASS_MUX0:
1023 case E_GOP_IP0_SUB_MUX:
1024 case E_GOP_VOP0_SUB_MUX:
1025 case E_GOP_OP1_MUX:
1026 case E_GOP_DIP_MUX:
1027 case E_GOP_GS_MUX:
1028 case E_GOP_Mix_MUX0:
1029 case E_GOP_Mix_MUX1:
1030 case E_GOP_VE0_MUX:
1031 case E_GOP_VE1_MUX:
1032 default:
1033 break;
1034 }
1035 }
1036
HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,Gop_MuxSel eGopMux)1037 void HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8 u8GOPNum, Gop_MuxSel eGopMux)
1038 {
1039 switch(eGopMux)
1040 {
1041 case E_GOP_MUX0:
1042 case E_GOP_MUX1:
1043 case E_GOP_MUX2:
1044 case E_GOP_IP0_MUX:
1045 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
1046 break;
1047 case E_GOP_MUX3:
1048 case E_GOP_IP1_MUX:
1049 case E_GOP_VOP0_MUX:
1050 case E_GOP_VOP1_MUX:
1051 case E_GOP_FRC_MUX0:
1052 case E_GOP_FRC_MUX1:
1053 case E_GOP_FRC_MUX2:
1054 case E_GOP_FRC_MUX3:
1055 case E_GOP_BYPASS_MUX0:
1056 case E_GOP_IP0_SUB_MUX:
1057 case E_GOP_VOP0_SUB_MUX:
1058 case E_GOP_OP1_MUX:
1059 case E_GOP_DIP_MUX:
1060 case E_GOP_GS_MUX:
1061 case E_GOP_Mix_MUX0:
1062 case E_GOP_Mix_MUX1:
1063 case E_GOP_VE0_MUX:
1064 case E_GOP_VE1_MUX:
1065 default:
1066 break;
1067 }
1068 }
1069
HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1070 GOP_Result HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1071 {
1072 /* GOP OP Path enable to SC Setting
1073 A5: GOP OP Path blending with SC sequence
1074 mux1-->mux0-->mux2-->mux3
1075 */
1076 MS_U16 muxValue=0, regval=0;
1077
1078 if(gopNum >= MAX_GOP_SUPPORT)
1079 {
1080 GOP_H_ERR("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum);
1081 return GOP_FAIL;
1082 }
1083
1084 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1085 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, ®val);
1086
1087 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1088 {
1089 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT15):(regval & ~GOP_BIT15), GOP_BIT15);
1090 }
1091
1092 if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1093 {
1094 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval | GOP_BIT14):(regval & ~GOP_BIT14), GOP_BIT14);
1095 }
1096
1097 if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1098 {
1099 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT13):(regval & ~GOP_BIT13), GOP_BIT13);
1100 }
1101
1102 return GOP_SUCCESS;
1103 }
1104
HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1105 GOP_Result HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1106 {
1107 /* GOP OP Path enable to SC Setting
1108 A5: GOP OP Path blending with SC sequence
1109 mux1-->mux0-->mux2-->mux3
1110 */
1111 MS_U16 muxValue=0, regval=0;
1112
1113 if(gopNum >= MAX_GOP_SUPPORT)
1114 {
1115 GOP_H_ERR("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum );
1116 return FALSE;
1117 }
1118
1119 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1120 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1121 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1122 {
1123 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x10):(regval & ~0x10), 0x30);
1124 }
1125 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1126 {
1127 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x40):(regval & ~0x40), 0xC0);
1128 }
1129 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1130 {
1131 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x100):(regval & ~0x100), 0x300);
1132 }
1133 else
1134 {
1135 return GOP_FAIL;
1136 }
1137 return GOP_SUCCESS;
1138 }
1139
HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL * pbEnable)1140 GOP_Result HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL *pbEnable)
1141 {
1142 MS_U16 muxValue=0, regval=0;
1143
1144 if(gopNum >= MAX_GOP_SUPPORT)
1145 {
1146 GOP_H_ERR("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum );
1147 return FALSE;
1148 }
1149
1150 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1151 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1152 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1153 {
1154 *pbEnable = (regval & GOP_BIT4) == GOP_BIT4;
1155 }
1156 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1157 {
1158 *pbEnable = (regval & GOP_BIT6) == GOP_BIT6;
1159 }
1160 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1161 {
1162 *pbEnable = (regval & GOP_BIT8) == GOP_BIT8;
1163 }
1164 else
1165 {
1166 return GOP_FAIL;
1167 }
1168 return GOP_SUCCESS;
1169 }
1170
HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum)1171 GOP_Result HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum)
1172 {
1173 /*T8
1174 OP path: support 4 mux (mux0, mux1, mux 2, mux3) to blend with SC simultaneously
1175 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1176 */
1177 MS_U16 Mux3Gop, muxValue=0, i;
1178 MS_U16 MuxShift;
1179
1180 MuxShift = GOP_MUX_SHIFT * E_GOP_MUX2;
1181
1182 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1183 for (i=0; i<MAX_GOP_MUX;i++) //T8 4 mux
1184 {
1185 if (gopNum== ((muxValue&(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)))>>(i*GOP_MUX_SHIFT)))
1186 {
1187 Mux3Gop = (muxValue&GOP_MUX2_MASK)>> MuxShift; //save mux2 gop
1188
1189 muxValue &= ~GOP_MUX2_MASK; //clear mux2 setting
1190 muxValue &= ~(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)); //clear current mux setting
1191 muxValue |= ((gopNum<< MuxShift)|(Mux3Gop<<(i*GOP_MUX_SHIFT)));
1192 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, muxValue, GOP_REG_WORD_MASK);
1193 break;
1194
1195 }
1196
1197 }
1198 return GOP_SUCCESS;
1199 }
1200
HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,DRV_GOPDstType eDstType)1201 GOP_Result HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, DRV_GOPDstType eDstType)
1202 {
1203 /*T8 GOP dst type:
1204 0: IP (Main)
1205 1: IP (Sub)
1206 2: OP
1207 3: MVOP
1208 */
1209
1210 /* Monaco clkgen setting */
1211 /******************
1212 0: odclk
1213 1: idclk_f2 (ipm)
1214 2: idclk_f1 (ips)
1215 3: ocmixer
1216 4: ve
1217 5 : mvop main
1218 6 : mvop sub
1219 ******************/
1220 if(gopNum >= MAX_GOP_SUPPORT)
1221 {
1222 GOP_H_FATAL("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum);
1223 MS_ASSERT(0);
1224 return GOP_INVALID_PARAMETERS;
1225 }
1226
1227 switch(eDstType)
1228 {
1229 case E_DRV_GOP_DST_IP0:
1230 if (gopNum==E_GOP1)
1231 {
1232 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1233 }
1234 else if (gopNum ==E_GOP2)
1235 {
1236 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
1237 }
1238 else if (gopNum==E_GOP0)
1239 {
1240 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1241 }
1242 else
1243 {
1244 MS_ASSERT(0);
1245 return GOP_INVALID_PARAMETERS;
1246 }
1247 break;
1248
1249 case E_DRV_GOP_DST_IP0_SUB:
1250 if (gopNum==E_GOP1)
1251 {
1252 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG1_MASK);
1253 }
1254 else if (gopNum==E_GOP2)
1255 {
1256 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK1, CKG_GOPG2_MASK);
1257 }
1258 else if (gopNum==E_GOP0)
1259 {
1260 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK1, CKG_GOPG0_MASK);
1261 }
1262 else
1263 {
1264 MS_ASSERT(0);
1265 return GOP_INVALID_PARAMETERS;
1266 }
1267 break;
1268
1269 case E_DRV_GOP_DST_OP0:
1270 if (gopNum==E_GOP1)
1271 {
1272 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_ODCLK, CKG_GOPG1_MASK);
1273 }
1274 else if (gopNum==E_GOP2)
1275 {
1276 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_ODCLK, CKG_GOPG2_MASK);
1277 }
1278 else if (gopNum==E_GOP0)
1279 {
1280 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_ODCLK, CKG_GOPG0_MASK);
1281 }
1282 else
1283 {
1284 MS_ASSERT(0);
1285 return GOP_INVALID_PARAMETERS;
1286 }
1287 break;
1288
1289 case E_DRV_GOP_DST_VOP:
1290 if (gopNum==E_GOP1)
1291 {
1292 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1293 }
1294 else if (gopNum ==E_GOP2)
1295 {
1296 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
1297 }
1298 else if (gopNum==E_GOP0)
1299 {
1300 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1301 }
1302 else
1303 {
1304 MS_ASSERT(0);
1305 return GOP_INVALID_PARAMETERS;
1306 }
1307 break;
1308
1309 default:
1310 MS_ASSERT(0);
1311 return GOP_ENUM_NOT_SUPPORTED;
1312 }
1313 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &pGOPHalLocal->u16Clk0Setting); //Backup current GOPG clock settings
1314 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK,&pGOPHalLocal->u16Clk2Setting); //Backup current SRAM clock settings
1315
1316 return GOP_SUCCESS;
1317 }
1318
1319
HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)1320 GOP_Result HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
1321 {
1322 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, GOP_BIT8);
1323 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
1324 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_ODCLK, CKG_GOPD_MASK);
1325 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
1326 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_DC0CLK, CKG_GOPD_MASK);
1327 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
1328 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_IDCLK2, CKG_GOPD_MASK);
1329 else
1330 return GOP_INVALID_PARAMETERS;
1331
1332 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &pGOPHalLocal->u16Clk1Setting); //Backup current GOPD clock settings
1333 return GOP_SUCCESS;
1334 }
HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)1335 GOP_Result HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_BOOL bEnable)
1336 {
1337 if (bEnable)
1338 {
1339 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOPHalLocal->u16Clk0Setting, GOP_REG_WORD_MASK);
1340 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOPHalLocal->u16Clk1Setting, GOP_REG_WORD_MASK);
1341 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOPHalLocal->u16Clk2Setting, GOP_REG_WORD_MASK);
1342 }
1343 else
1344 {
1345 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_DISABLE_CLK, CKG_GOPG0_MASK);
1346 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_DISABLE_CLK, CKG_GOPG1_MASK);
1347 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_DISABLE_CLK, CKG_GOPG2_MASK);
1348 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_DISABLE_CLK, CKG_GOPD_MASK);
1349 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM0_DISABLE_CLK, CKG_SRAM0_MASK);
1350 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM1_DISABLE_CLK, CKG_SRAM1_MASK);
1351 }
1352
1353 return GOP_SUCCESS;
1354 }
1355
HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1356 GOP_Result HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1357 {
1358 return GOP_FUN_NOT_SUPPORTED;
1359 }
1360
HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_U8 muxNum,MS_BOOL bEnable)1361 GOP_Result HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_U8 muxNum, MS_BOOL bEnable)
1362 {
1363 return GOP_FUN_NOT_SUPPORTED;
1364 }
1365
HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)1366 GOP_Result HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEn)
1367 {
1368 return GOP_FUN_NOT_SUPPORTED;
1369 }
1370
HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_CTX_HAL_SHARED * pHALShared,MS_BOOL bNeedInitShared)1371 void HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_CTX_HAL_SHARED *pHALShared, MS_BOOL bNeedInitShared)
1372 {
1373 MS_U32 u32GopIdx;
1374
1375 memset(pGOPHalLocal, 0, sizeof(*pGOPHalLocal));
1376 pGOPHalLocal->pHALShared = pHALShared;
1377
1378 for(u32GopIdx=0; u32GopIdx<MAX_GOP_SUPPORT; u32GopIdx++)
1379 {
1380 pGOPHalLocal->drvGFlipGOPDst[u32GopIdx] = E_DRV_GOP_DST_OP0;
1381 #ifdef GOP_VSTRETCH_OLD_MODE
1382 pGOPHalLocal->pHALShared->u16GOPSrcHeight[u32GopIdx]=GOP_VSTRETCH_DEFAULT_SIZE;
1383 #endif
1384 }
1385 pGOPHalLocal->pGopChipPro = &pHALShared->gopChipProperty;
1386 pGOPHalLocal->pbIsMuxVaildToGopDst = (MS_BOOL *)bIsMuxVaildToGopDst;
1387 }
HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1388 void HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1389 {
1390 }
1391
HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,MS_PHY * u64Adr)1392 GOP_Result HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gwinid, MS_PHY* u64Adr)
1393 {
1394 MS_U8 u8Miu=0xff;
1395 MS_U16 u16RegVal=0;
1396
1397 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal);
1398 if (gwinid<MAX_GOP0_GWIN) //gop0
1399 {
1400 u16RegVal &= BIT(GOP_MIU_CLIENT_GOP0);
1401 u8Miu = (u16RegVal>>GOP_MIU_CLIENT_GOP0);
1402 }
1403 else if (gwinid>=MAX_GOP0_GWIN && gwinid<MAX_GOP0_GWIN+MAX_GOP1_GWIN) //gop1
1404 {
1405 u16RegVal &= BIT(GOP_MIU_CLIENT_GOP1);
1406 u8Miu = (u16RegVal>>GOP_MIU_CLIENT_GOP1);
1407 }
1408 else if (gwinid==GOP2_GwinIdBase) //gop2
1409 {
1410 u16RegVal &= BIT(GOP_MIU_CLIENT_GOP2);
1411 u8Miu = (u16RegVal>>GOP_MIU_CLIENT_GOP2);
1412 }
1413 else
1414 {
1415 return GOP_FAIL;
1416 }
1417
1418 if (u8Miu < 2)
1419 {
1420 _miu_offset_to_phy(u8Miu, *u64Adr, *u64Adr);
1421 }
1422 else
1423 {
1424 GOP_H_ERR("[%s] ERROR GOP miu client\n",__FUNCTION__);
1425 return GOP_FAIL;
1426 }
1427 return GOP_SUCCESS;
1428 }
HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopnum)1429 MS_U8 HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopnum)
1430 {
1431 MS_U8 u8Miu=0xff;
1432 MS_U16 u16RegVal=0;
1433 MS_U32 u32BnkOfst=0xFFFF;
1434
1435 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[gopnum]==TRUE)
1436 {
1437 _GetBnkOfstByGop(gopnum, &u32BnkOfst);
1438 HAL_GOP_Read16Reg(pGOPHalLocal, u32BnkOfst+GOP_4G_MIU_SEL, &u16RegVal);
1439 u8Miu= u16RegVal& (GOP_BIT0|GOP_BIT1);
1440 }
1441 else
1442 {
1443 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal);
1444 switch (gopnum)
1445 {
1446 case 0:
1447 u16RegVal &= BIT(GOP_MIU_CLIENT_GOP0);
1448 u8Miu = (u16RegVal>>GOP_MIU_CLIENT_GOP0);
1449 break;
1450 case 1:
1451 u16RegVal &= BIT(GOP_MIU_CLIENT_GOP1);
1452 u8Miu = (u16RegVal>>GOP_MIU_CLIENT_GOP1);
1453 break;
1454
1455 case 2:
1456 u16RegVal &= BIT(GOP_MIU_CLIENT_GOP2);
1457 u8Miu = (u16RegVal>>GOP_MIU_CLIENT_GOP2);
1458 break;
1459
1460 default:
1461 return 0xff;
1462 break;
1463 }
1464
1465 if(u8Miu > MAX_GOP_MIUSEL )
1466 {
1467 GOP_H_ERR("[%s] ERROR GOP miu client\n",__FUNCTION__);
1468 return 0xff;
1469 }
1470
1471 }
1472 return u8Miu;
1473 }
HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8gopNum,DRV_GOPDstType * pGopDst)1474 GOP_Result HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8gopNum, DRV_GOPDstType *pGopDst)
1475 {
1476 MS_U16 u16Regval;
1477 MS_U32 u32pBankOffSet=0;
1478 GOP_Result ret;
1479
1480 if(u8gopNum >= MAX_GOP_SUPPORT)
1481 {
1482 GOP_H_ERR("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8gopNum);
1483 *pGopDst = E_DRV_GOP_DST_INVALID;
1484 return GOP_FAIL;
1485 }
1486
1487 _GetBnkOfstByGop(u8gopNum, &u32pBankOffSet);
1488 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_CTRL1, &u16Regval);
1489
1490 switch (u16Regval&GOP_DST_MASK)
1491 {
1492 case 0:
1493 *pGopDst = E_DRV_GOP_DST_IP0;
1494 ret = GOP_SUCCESS;
1495 break;
1496 case 1:
1497 *pGopDst = E_DRV_GOP_DST_IP0_SUB;
1498 ret = GOP_SUCCESS;
1499 break;
1500 case 2:
1501 *pGopDst = E_DRV_GOP_DST_OP0;
1502 ret = GOP_SUCCESS;
1503 break;
1504 default:
1505 *pGopDst = E_DRV_GOP_DST_INVALID;
1506 ret = GOP_FAIL;
1507 break;
1508 }
1509
1510 return ret;
1511
1512 }
1513
HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_IPSEL_GOP ipSelGop)1514 void HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_IPSEL_GOP ipSelGop)
1515 {
1516 MS_U16 muxValue=0;
1517 MS_U16 u16RegVal= 0, u16RegMsk = 0;
1518
1519 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1520
1521 switch(ipSelGop)
1522 {
1523 case MS_DRV_IP0_SEL_GOP0:
1524 u16RegVal = GOP_BIT15|GOP_BIT7 | GOP_BIT5 ;
1525 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
1526 u16RegVal |= GOP_BIT12;//mux0
1527 else
1528 u16RegVal |= GOP_BIT13;//mux1
1529 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
1530 break;
1531
1532 case MS_DRV_IP0_SEL_GOP1:
1533 u16RegVal = GOP_BIT15|GOP_BIT7 | GOP_BIT5 ;
1534 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
1535 u16RegVal |= GOP_BIT12;//mux0
1536 else
1537 u16RegVal |= GOP_BIT13;//mux1
1538 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
1539 break;
1540 case MS_DRV_IP0_SEL_GOP2:
1541 u16RegVal = GOP_BIT15|GOP_BIT7 | GOP_BIT5 ;
1542 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
1543 u16RegVal |= GOP_BIT12;//mux0
1544 else
1545 u16RegVal |= GOP_BIT13;//mux1
1546 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
1547 break;
1548
1549 case MS_DRV_NIP_SEL_GOP0:
1550 if( (g_GopChipPro.bNeedSetMUX1ToIP0 && (E_GOP0 == ((muxValue &GOP_MUX1_MASK)>>GOP_MUX_SHIFT)))
1551 ||(g_GopChipPro.bNeedSetMUX3ToIP0 && (E_GOP0 == ((muxValue &GOP_MUX3_MASK)>>GOP_MUX_SHIFT*3))))
1552 {
1553 u16RegVal |= GOP_BIT11; //Disable IP if IPMUX=GOP0
1554 u16RegMsk |= GOP_BIT11;
1555 }
1556 break;
1557
1558 case MS_DRV_NIP_SEL_GOP1:
1559 if( (g_GopChipPro.bNeedSetMUX1ToIP0 && (E_GOP1 == ((muxValue &GOP_MUX1_MASK)>>GOP_MUX_SHIFT)))
1560 ||(g_GopChipPro.bNeedSetMUX3ToIP0 && (E_GOP1 == ((muxValue &GOP_MUX3_MASK)>>GOP_MUX_SHIFT*3))))
1561 {
1562 u16RegVal |= GOP_BIT11; //Disable IP if IPMUX=GOP0
1563 u16RegMsk |= GOP_BIT11;
1564 }
1565 break;
1566
1567 case MS_DRV_NIP_SEL_GOP2:
1568 if( (g_GopChipPro.bNeedSetMUX1ToIP0 && (E_GOP2 == ((muxValue &GOP_MUX1_MASK)>>GOP_MUX_SHIFT)))
1569 ||(g_GopChipPro.bNeedSetMUX3ToIP0 && (E_GOP2 == ((muxValue &GOP_MUX3_MASK)>>GOP_MUX_SHIFT*3))))
1570 {
1571 u16RegVal |= GOP_BIT11; //Disable IP if IPMUX=GOP0
1572 u16RegMsk |= GOP_BIT11;
1573 }
1574 break;
1575
1576 case MS_DRV_MVOP_SEL:
1577 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
1578 u16RegVal |= GOP_BIT12; //mux0
1579 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
1580 break;
1581 default:
1582 GOP_H_ERR("[%s] ERROR invalid source select\n",__FUNCTION__);
1583 break;
1584 }
1585 if(0 != u16RegMsk)
1586 {
1587 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, u16RegVal, u16RegMsk);
1588 }
1589 }
1590
HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)1591 GOP_Result HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
1592 {
1593 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
1594 {
1595 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_CTL0_EN, 0, (GOP_BIT8|GOP_BIT9));
1596 }
1597 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
1598 {
1599 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_CTL0_EN, (GOP_BIT8|GOP_BIT9), (GOP_BIT8|GOP_BIT9));
1600 }
1601 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
1602 {
1603 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_CTL0_EN, (GOP_BIT8), (GOP_BIT8|GOP_BIT9));
1604 //enable scaler IP.
1605 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT12, GOP_BIT12|GOP_BIT13);
1606 // set GOPD to scaler ip OUT
1607 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, GOP_BIT15, GOP_BIT15);
1608 }
1609 else
1610 {
1611 return GOP_INVALID_PARAMETERS;
1612 }
1613
1614 return GOP_SUCCESS;
1615 }
1616
1617
HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1618 MS_U8 HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1619 {
1620 MS_U16 u16RegVal=0;
1621 MS_U16 mask_shift=0;
1622
1623
1624 if (GOP_MIU_CLIENT_DWIN >=0x10)
1625 {
1626 MS_CRITICAL_MSG(GOP_H_ERR(" %s :DWIN is not support\n",__FUNCTION__));
1627 return GOP_FAIL;
1628 }
1629 else
1630 mask_shift = GOP_MIU_CLIENT_DWIN;
1631
1632 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal);
1633 return ((u16RegVal&(1<<mask_shift))? MIU_1:MIU_0);
1634
1635 }
HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 miu)1636 GOP_Result HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 miu)
1637 {
1638 MS_U16 mask_shift=0;
1639
1640 if ( (miu>2) || (GOP_MIU_CLIENT_DWIN >= 0x10))
1641 {
1642 MS_CRITICAL_MSG(GOP_H_ERR(" %s :DWIN is not support\n",__FUNCTION__));
1643 return GOP_FAIL;
1644 }
1645 else
1646 mask_shift = GOP_MIU_CLIENT_DWIN;
1647
1648 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, miu<<mask_shift, 1<<mask_shift);
1649
1650 return GOP_SUCCESS;
1651
1652
1653 }
1654
HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)1655 GOP_Result HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable)
1656 {
1657 if (bEnable)
1658 {
1659 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_ALPHA, GOP_BIT6, GOP_BIT6);
1660 }
1661 else
1662 {
1663 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_ALPHA, ~GOP_BIT6, GOP_BIT6);
1664 }
1665 return GOP_SUCCESS;
1666 }
1667
HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode)1668 GOP_Result HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode)
1669 {
1670 return GOP_FUN_NOT_SUPPORTED;
1671 }
1672
HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode,GOP_DRV_MixerTiming * pTM)1673 GOP_Result HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode, GOP_DRV_MixerTiming *pTM)
1674 {
1675 return GOP_FUN_NOT_SUPPORTED;
1676 }
1677
HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEn)1678 GOP_Result HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEn)
1679 {
1680 return GOP_FUN_NOT_SUPPORTED;
1681 }
1682
HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,E_GOP_TILE_DATA_TYPE tilemode)1683 GOP_Result HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, E_GOP_TILE_DATA_TYPE tilemode)
1684 {
1685 return GOP_FUN_NOT_SUPPORTED;
1686 }
1687
1688
HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)1689 GOP_Result HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
1690 {
1691 MS_U32 u32BankOffSet =0;
1692
1693 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
1694
1695 if (bEn)
1696 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT14, GOP_BIT14);
1697 else
1698 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, ~GOP_BIT14, GOP_BIT14);
1699
1700 return GOP_SUCCESS;
1701 }
1702
HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)1703 GOP_Result HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
1704 {
1705 MS_U32 u32BankOffSet =0;
1706
1707 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
1708
1709 if (bEn)
1710 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT15, GOP_BIT15);
1711 else
1712 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, 0x0, GOP_BIT15);
1713
1714 return GOP_SUCCESS;
1715 }
1716
HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL * pEnable)1717 GOP_Result HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL* pEnable)
1718 {
1719 MS_U16 u16Val =0x0;
1720 if (u8win < GOP1_GwinIdBase)
1721 {
1722 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), &u16Val);
1723 *pEnable = (MS_BOOL)(u16Val>>15);
1724 }
1725 else if (u8win < GOP2_GwinIdBase)
1726 {
1727 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), &u16Val);
1728 *pEnable = (MS_BOOL)(u16Val>>15);
1729 }
1730 else if (u8win < GOP3_GwinIdBase)
1731 {
1732 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, &u16Val);
1733 *pEnable = (MS_BOOL)(u16Val>>15);
1734 }
1735 else if (u8win < GOP4_GwinIdBase)
1736 {
1737 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, &u16Val);
1738 *pEnable = (MS_BOOL)(u16Val>>15);
1739 }
1740 else if (u8win < GOP5_GwinIdBase)
1741 {
1742 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, &u16Val);
1743 *pEnable = (MS_BOOL)(u16Val>>15);
1744 }
1745 else
1746 {
1747 GOP_H_ERR("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
1748 return GOP_INVALID_PARAMETERS;
1749 }
1750
1751 return GOP_SUCCESS;
1752 }
1753
HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable)1754 GOP_Result HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable)
1755 {
1756 return GOP_FUN_NOT_SUPPORTED;
1757 }
1758
HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8Gwin,MS_PHY u32SubAddr)1759 GOP_Result HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP ,MS_U8 u8Gwin, MS_PHY u32SubAddr)
1760 {
1761 MS_U16 u16Reg = 0;
1762 MS_U32 u32WordBase = 0;
1763 MS_U32 u32BankOffSet=0;
1764
1765 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
1766
1767 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_FWR, &u16Reg);
1768
1769 if(u16Reg & GOP_BIT7)
1770 {
1771 u32WordBase = 1;
1772 }
1773 else
1774 {
1775 u32WordBase = GOP_WordUnit;
1776 }
1777
1778 u32SubAddr /= u32WordBase;
1779
1780 if(u8GOP == E_GOP2)
1781 {
1782 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
1783 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
1784 }
1785 else if(u8GOP == E_GOP1)
1786 {
1787 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_L(u8Gwin - MAX_GOP0_GWIN), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
1788 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_H(u8Gwin - MAX_GOP0_GWIN), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
1789 }
1790 else //gop0
1791 {
1792 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_L(u8Gwin), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
1793 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_H(u8Gwin), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
1794 }
1795
1796 return GOP_SUCCESS;
1797
1798 }
1799
1800 //------------------------------------------------------------------------------
1801 /// Set VE output with OSD
1802 /// @return none
1803 //------------------------------------------------------------------------------
HAL_GOP_VE_SetOSDEnable(MS_BOOL bEnable,EN_VE_OSD_ENABLE eOSD,MS_U8 gopNum)1804 GOP_Result HAL_GOP_VE_SetOSDEnable(MS_BOOL bEnable, EN_VE_OSD_ENABLE eOSD, MS_U8 gopNum)
1805 {
1806 return GOP_FUN_NOT_SUPPORTED;
1807 }
1808
HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEn)1809 GOP_Result HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEn )
1810 {
1811 return GOP_FUN_NOT_SUPPORTED;
1812 }
1813
HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bHorizontal)1814 E_GOP_VIDEOTIMING_MIRRORTYPE HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bHorizontal)
1815 {
1816 E_GOP_VIDEOTIMING_MIRRORTYPE enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
1817 MS_U16 u16MVOPMirrorCfg = 0;
1818 MS_U16 u16ScalerMirrorCfg = 0;
1819
1820 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MVOP_MIRRORCFG, &u16MVOPMirrorCfg);
1821 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &u16ScalerMirrorCfg);
1822 if(bHorizontal) // Horizontal
1823 {
1824 if(u16MVOPMirrorCfg & GOP_BIT1)
1825 {
1826 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
1827 }
1828 else if(u16ScalerMirrorCfg & GOP_BIT12)
1829 {
1830 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
1831 }
1832 }
1833 else //vertical
1834 {
1835 if(u16MVOPMirrorCfg & GOP_BIT0)
1836 {
1837 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
1838 }
1839 else if(u16ScalerMirrorCfg & GOP_BIT13)
1840 {
1841 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
1842 }
1843 }
1844 return enMirrorType;
1845 }
1846
HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)1847 GOP_Result HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)
1848 {
1849 return GOP_FUN_NOT_SUPPORTED;
1850 }
1851
HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bOCEn)1852 GOP_Result HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bOCEn)
1853 {
1854 return GOP_FUN_NOT_SUPPORTED;
1855 }
1856
HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_OC_INFO * pOCinfo)1857 GOP_Result HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_OC_INFO* pOCinfo)
1858 {
1859 return GOP_FUN_NOT_SUPPORTED;
1860 }
1861
HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * MIUId)1862 GOP_Result HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 *MIUId)
1863 {
1864 return GOP_FUN_NOT_SUPPORTED;
1865 }
1866
HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32RingSize,MS_U32 u32BufSize)1867 GOP_Result HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32RingSize,MS_U32 u32BufSize)
1868 {
1869 MS_U16 u16BufCnt=0;
1870 u16BufCnt = u32BufSize/u32RingSize;
1871 HAL_GOP_Write32Reg(pGOPHalLocal, GOP_DW_FRAME_OFT_L,u32RingSize);
1872 if(u16BufCnt == 0)
1873 {
1874 GOP_H_DBUG("!!!Alert !!! DWIN Capture,mem size is not enought!\n");
1875 }else{
1876 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_FRAME_CTRL,u16BufCnt-1, 0xF);
1877 }
1878 return GOP_SUCCESS;
1879 }
1880
HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType)1881 GOP_Result HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType)
1882 {
1883 return GOP_FUN_NOT_SUPPORTED;
1884 }
1885
1886 /********************************************************************************/
1887 ///Test Pattern
1888 /********************************************************************************/
HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)1889 GOP_Result HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
1890 {
1891 if(u8GopNum == pGOPHalLocal->pGopChipPro->GOP_TestPattern_Vaild)
1892 {
1893 return GOP_SUCCESS;
1894 }
1895 else
1896 {
1897 return GOP_FAIL;
1898 }
1899
1900 }
1901
1902
1903 /********************************************************************************/
1904 ///GOP Scaling down (internal)
1905 /********************************************************************************/
1906
HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)1907 MS_BOOL HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)
1908 {
1909 return GOP_FUN_NOT_SUPPORTED;
1910 }
1911
HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)1912 GOP_Result HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
1913 {
1914 return GOP_FUN_NOT_SUPPORTED;
1915 }
1916
HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)1917 GOP_Result HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
1918 {
1919 return GOP_FUN_NOT_SUPPORTED;
1920 }
1921
HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16HSize,MS_U16 u16VSize)1922 GOP_Result HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_U16 u16HSize, MS_U16 u16VSize)
1923 {
1924 MS_U32 u32BankOffSet=0;
1925
1926 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
1927 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_HVAILDSIZE, u16HSize, GOP_REG_WORD_MASK);
1928 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_VVAILDSIZE, u16VSize, GOP_REG_WORD_MASK);
1929 return GOP_SUCCESS;
1930 }
1931
HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 * u16Val)1932 GOP_Result HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16* u16Val)
1933 {
1934 MS_U32 u32BankOffSet=0;
1935 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
1936
1937 if (u32GopIdx < MAX_GOP_SUPPORT)
1938 {
1939 HAL_GOP_Read16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val);
1940 }
1941 else
1942 {
1943 GOP_H_ERR("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
1944 *u16Val = 0;
1945 }
1946 return GOP_SUCCESS;
1947 }
1948
HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 u16Val)1949 GOP_Result HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16 u16Val)
1950 {
1951 MS_U32 u32BankOffSet=0;
1952 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
1953
1954 if (u32GopIdx < MAX_GOP_SUPPORT)
1955 {
1956 HAL_GOP_Write16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val, GOP_REG_WORD_MASK);
1957 }
1958 else
1959 {
1960 GOP_H_ERR("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
1961 }
1962 return GOP_SUCCESS;
1963 }
1964
HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32PowerState,GFLIP_REGS_SAVE_AREA * pGOP_STRPrivate)1965 GOP_Result HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32PowerState, GFLIP_REGS_SAVE_AREA* pGOP_STRPrivate)
1966 {
1967 switch(u32PowerState)
1968 {
1969 case E_POWER_SUSPEND:
1970 {
1971 //CLK
1972 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &(pGOP_STRPrivate->CKG_GopReg[0]));
1973 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &(pGOP_STRPrivate->CKG_GopReg[1]));
1974 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[4]));
1975
1976 //XC
1977 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &(pGOP_STRPrivate->XC_GopReg[0]));
1978 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[1]));
1979 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, &(pGOP_STRPrivate->XC_GopReg[2]));
1980 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, &(pGOP_STRPrivate->XC_GopReg[3]));
1981 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, &(pGOP_STRPrivate->XC_GopReg[4]));
1982 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, &(pGOP_STRPrivate->XC_GopReg[5]));
1983 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOPNBL, &(pGOP_STRPrivate->XC_GopReg[6]));
1984 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, &(pGOP_STRPrivate->XC_GopReg[7]));
1985 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &(pGOP_STRPrivate->XC_GopReg[8]));
1986 }
1987 break;
1988 case E_POWER_RESUME:
1989 {
1990 //CLK
1991 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOP_STRPrivate->CKG_GopReg[0], GOP_REG_WORD_MASK);
1992 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOP_STRPrivate->CKG_GopReg[1], GOP_REG_WORD_MASK);
1993 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[4], GOP_REG_WORD_MASK);
1994
1995 //XC
1996 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, pGOP_STRPrivate->XC_GopReg[0], GOP_REG_WORD_MASK);
1997 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[1], GOP_BIT11);
1998 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, pGOP_STRPrivate->XC_GopReg[2], GOP_REG_WORD_MASK);
1999 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, pGOP_STRPrivate->XC_GopReg[3], GOP_REG_WORD_MASK);
2000 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, pGOP_STRPrivate->XC_GopReg[4], GOP_BIT15);
2001 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, pGOP_STRPrivate->XC_GopReg[5], GOP_BIT6);
2002 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOPNBL, pGOP_STRPrivate->XC_GopReg[6], GOP_BIT5);
2003 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, pGOP_STRPrivate->XC_GopReg[7], GOP_REG_WORD_MASK);
2004 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, pGOP_STRPrivate->XC_GopReg[8], GOP_REG_WORD_MASK);
2005 }
2006 break;
2007 default:
2008 break;
2009 }
2010 return GOP_SUCCESS;
2011 }
HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,EN_DRV_GOP_GPU_TILE_MODE tile_mode)2012 GOP_Result HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gwinid, EN_DRV_GOP_GPU_TILE_MODE tile_mode)
2013 {
2014 return GOP_FUN_NOT_SUPPORTED;
2015 }
2016
HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)2017 GOP_Result HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable)
2018 {
2019 return GOP_FUN_NOT_SUPPORTED;
2020 }
2021
HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr,MS_U32 u32size)2022 GOP_Result HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr, MS_U32 u32size)
2023 {
2024 return GOP_FUN_NOT_SUPPORTED;
2025 }
2026
HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr)2027 GOP_Result HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr)
2028 {
2029 return GOP_FUN_NOT_SUPPORTED;
2030 }
2031
HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)2032 GOP_Result HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
2033 {
2034 return GOP_FUN_NOT_SUPPORTED;
2035 }
2036
HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)2037 GOP_Result HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
2038 {
2039 MS_U32 u32BankOffSet=0xFFFF;
2040 MS_U16 mask_shift=0xFF;
2041
2042 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2043 switch(u8GOP)
2044 {
2045 case E_GOP0:
2046 mask_shift = GOP_MIU_CLIENT_GOP0;
2047 break;
2048 case E_GOP1:
2049 mask_shift = GOP_MIU_CLIENT_GOP1;
2050 break;
2051 case E_GOP2:
2052 mask_shift = GOP_MIU_CLIENT_GOP2;
2053 break;
2054 default:
2055 mask_shift = 0xFF;
2056 MS_CRITICAL_MSG(GOP_H_DBUG("ERROR gop miu client\n"));
2057 break;
2058 }
2059
2060 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, miusel<<mask_shift, 1<<mask_shift );
2061
2062 return GOP_SUCCESS;
2063 }
2064
2065 #ifdef GOP_CMDQ_ENABLE
HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * cmdq_struct,MS_U32 * number,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)2066 GOP_Result HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *cmdq_struct,MS_U32 *number,MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
2067 {
2068 MS_U16 u16xcSubbank=0;
2069 MS_U32 bank;
2070 MS_U32 direct_addr;
2071
2072 switch (u32addr & 0xFF00)
2073 {
2074 case GOP_REG_BASE:
2075 {
2076 bank = (u32addr & 0xFF0000) >> 8;
2077
2078 if(bank==0xE00)//GOP4: 0x121B00
2079 {
2080 bank=GOP_REG_GOP4_BK_OFFSET;
2081 }
2082 else if(bank==0xF00)//GWIN4: 0x121E00
2083 {
2084 bank=GOP_REG_GOP4_GW_OFFSET;
2085 }
2086 else if(bank==0x1000) //GOP4_ST
2087 {
2088 bank=GOP_REG_GOP4_ST_OFFSET;
2089 }
2090
2091 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
2092
2093 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
2094 cmdq_struct[(*number)].destionation_value = u16val;
2095 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
2096 cmdq_struct[(*number)].operation = 0x57;
2097 (*number)++;
2098 break;
2099 }
2100 case SC1_REG_BASE:
2101 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
2102 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
2103
2104 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
2105 cmdq_struct[(*number)].destionation_value = u16val;
2106 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
2107 cmdq_struct[(*number)].operation = 0x57;
2108 (*number)++;
2109 break;
2110 case GE_REG_BASE:
2111 case CKG_REG_BASE:
2112 case MIU_REG_BASE:
2113 {
2114 cmdq_struct[(*number)].destionation_address = (u32addr&0xFFFFF)+0x100000;
2115 cmdq_struct[(*number)].destionation_value = u16val;
2116 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
2117 cmdq_struct[(*number)].operation = 0x57;
2118 (*number)++;
2119 break;
2120 }
2121 default:
2122 {
2123 //Gop lib current do not support this HW ip base
2124 MS_ASSERT(0);
2125 break;
2126 }
2127
2128 }
2129 return GOP_SUCCESS;
2130 }
HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 * u32GopIdx)2131 GOP_Result HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 *u32GopIdx)
2132 {
2133 MS_U32 u32BankOffSet=0xFFFF;
2134 MS_U16 u16RegVal1 = 0;
2135 MS_BOOL bCheckValidGop = FALSE;
2136 MS_U8 u8CheckTimeCnt = 0;
2137 MS_U8 u8CurrentCmdGop = 0;
2138
2139 while (!bCheckValidGop && (u8CheckTimeCnt < (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0 + 2)))
2140 {
2141 if (u8CurrentCmdGop > (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0))
2142 {
2143 u8CurrentCmdGop = 0;
2144 }
2145 _GetBnkOfstByGop(u8CurrentCmdGop, &u32BankOffSet);
2146 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, &u16RegVal1);
2147 if ((u16RegVal1 & GOP_BIT0) != 0) // gop not init, cmdq won't work
2148 {
2149 bCheckValidGop = FALSE;
2150 }
2151 else
2152 {
2153 bCheckValidGop = TRUE;
2154 break;
2155 }
2156
2157 // if current gop not init, use next gop instead, check order 0->2->1->3
2158 switch (u8CurrentCmdGop)
2159 {
2160 case 0:
2161 u8CurrentCmdGop = 2;
2162 break;
2163 case 1:
2164 u8CurrentCmdGop = 0;
2165 break;
2166 case 2:
2167 u8CurrentCmdGop = 3;
2168 break;
2169 case 3:
2170 u8CurrentCmdGop = 1;
2171 break;
2172 default:
2173 u8CurrentCmdGop = 0;
2174 break;
2175 }
2176 u8CheckTimeCnt++;
2177 }
2178 if (!bCheckValidGop)
2179 {
2180 GOP_H_DBUG("[%s] Error message no avalible gop can support current cmdq!!\n",__FUNCTION__);
2181 }
2182
2183 *u32GopIdx = u8CurrentCmdGop;
2184 MDrv_CMDQ_Gen_WaitTrigger_Bus_Command(&(target[(*number)]),GOPG0_GOP_CMDQ_INT_0 + u8CurrentCmdGop,FALSE);
2185 (*number)++;
2186 return GOP_SUCCESS;
2187 }
HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 u32GopIdx)2188 GOP_Result HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 u32GopIdx)
2189 {
2190 CH_Struct ch_fire;
2191 MS_U32 Receive_Return_Value = 0,u32BankOffSet = 0,u32FireBankOffSet = 0,timer1 = 0x0,timer2 = 0x0;
2192 MS_U16 u16ret = 0,u16ret1 = 0;
2193 int i = 0;
2194
2195
2196 _GetBnkOfstByGop(0, &u32BankOffSet);
2197 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret);
2198 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,target,number,u32BankOffSet+GOP_4G_BG_CLR(1),u16ret+1,0xFFFF);//current GOP force write dis
2199 #if 0 //for Debug
2200 for(i=0;i<(*number);i++)
2201 {
2202 printf("\33[0;36m [%d]op = %d, addr = %lx,value = %x,mask = %x\33[m \n",i,target[i].operation,target[i].destionation_address,target[i].destionation_value,target[i].mask);
2203 }
2204 #endif
2205 ch_fire.Command_Number = *number;
2206 ch_fire.Pointer_To_CAFArray = target;
2207 Receive_Return_Value = MDrv_CMDQ_Receive(&ch_fire);
2208 if(Receive_Return_Value == DRVCMDQ_CMDQ_FULL)
2209 {
2210 Receive_Return_Value = 0;
2211 MDrv_CMDQ_Printf_Crash_Command();
2212 }
2213
2214 _GetBnkOfstByGop(u32GopIdx, &u32FireBankOffSet);
2215 MsOS_DelayTask(1);
2216 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT4, GOP_BIT4);//reset mask
2217 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, 0, GOP_BIT4); //reset nable detect
2218
2219 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
2220 timer1 = MsOS_GetSystemTime();
2221 timer2 = MsOS_GetSystemTime();
2222 while( u16ret1 != (u16ret+1) && ((timer2 - timer1)<100))
2223 {
2224 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
2225 MsOS_DelayTask(1);
2226 timer2 = MsOS_GetSystemTime();
2227 }
2228 if(u16ret1 != (u16ret+1)){
2229 printf("\33[0;36m %s:%d timeout = %ld org = %d target = %d\33[m \n",__FUNCTION__,__LINE__,(timer2 - timer1),u16ret1,(u16ret+1));
2230 MDrv_CMDQ_Printf_Crash_Command();
2231 }
2232 return GOP_SUCCESS;
2233 }
2234
HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)2235 GOP_Result HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
2236 {
2237 CAF_Struct fire_struct[24];
2238 MS_U32 u32BankOffSet=0xFFFF;
2239 MS_U32 number = 0;
2240 MS_U16 u16RegVal1 = 0,u16RegVal2 = 0,u16RegVal3 = 0,u16MiuClient = 0;
2241 MS_U32 fireGOP;
2242 _GetBnkOfstByGop(gop, &u32BankOffSet);
2243
2244 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal1);
2245 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
2246 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
2247
2248 switch(gop)
2249 {
2250 case E_GOP0:
2251 {
2252 u16MiuClient = GOP_MIU_CLIENT_GOP0;
2253 break;
2254 }
2255 case E_GOP1:
2256 {
2257 u16MiuClient = GOP_MIU_CLIENT_GOP1;
2258 break;
2259 }
2260 case E_GOP2:
2261 {
2262 u16MiuClient = GOP_MIU_CLIENT_GOP2;
2263 break;
2264 }
2265 default:
2266 {
2267 MS_ASSERT(0);
2268 break;
2269 }
2270 }
2271 if(bMIUSelect[gop] == TRUE)
2272 {
2273 if(u16MIUSelect[gop] == 0)
2274 {
2275 u16RegVal1 &= ~(1<<u16MiuClient);
2276 u16RegVal3 &= ~(1<<u16MiuClient);
2277 }
2278 else if(u16MIUSelect[gop] == 1)
2279 {
2280 u16RegVal1 |= (1<<u16MiuClient);
2281 u16RegVal3 &= ~(1<<u16MiuClient);
2282 }
2283 else if(u16MIUSelect[gop] == 2)
2284 {
2285 u16RegVal1 &= ~(1<<u16MiuClient);
2286 u16RegVal3 |= (1<<u16MiuClient);
2287 }
2288 else if(u16MIUSelect[gop] == 3)
2289 {
2290 u16RegVal1 |= (1<<u16MiuClient);
2291 u16RegVal3 |= (1<<u16MiuClient);
2292 }
2293 bMIUSelect[gop] = FALSE;
2294 }
2295 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
2296 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
2297 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_SC_MIU_SEL,u16RegVal1,0xFFFF);
2298 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
2299 return GOP_SUCCESS;
2300 }
2301
HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)2302 GOP_Result HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
2303 {
2304 CAF_Struct fire_struct[24];
2305 MS_U32 u32BankOffSet;
2306 MS_U32 number = 0;
2307 MS_U8 gop;
2308 MS_U16 u16RegVal1=0,u16RegVal2=0,u16RegVal3 = 0,u16MiuClient = 0;
2309 MS_U32 fireGOP;
2310
2311 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal1);
2312 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
2313
2314 for(gop = 0; gop<MAX_GOP_SUPPORT; gop++)
2315 {
2316 switch(gop)
2317 {
2318 case E_GOP0:
2319 {
2320 u16MiuClient = GOP_MIU_CLIENT_GOP0;
2321 break;
2322 }
2323 case E_GOP1:
2324 {
2325 u16MiuClient = GOP_MIU_CLIENT_GOP1;
2326 break;
2327 }
2328 case E_GOP2:
2329 {
2330 u16MiuClient = GOP_MIU_CLIENT_GOP2;
2331 break;
2332 }
2333 default:
2334 {
2335 continue;
2336 }
2337 }
2338 if( ( u16GopMask & (1<<gop) ) )
2339 {
2340 _GetBnkOfstByGop(gop, &u32BankOffSet);
2341 if(bMIUSelect[gop] == TRUE)
2342 {
2343 if(u16MIUSelect[gop] == 0)
2344 {
2345 u16RegVal1 &= ~(1<<u16MiuClient);
2346 u16RegVal3 &= ~(1<<u16MiuClient);
2347 }
2348 else if(u16MIUSelect[gop] == 1)
2349 {
2350 u16RegVal1 |= (1<<u16MiuClient);
2351 u16RegVal3 &= ~(1<<u16MiuClient);
2352 }
2353 else if(u16MIUSelect[gop] == 2)
2354 {
2355 u16RegVal1 &= ~(1<<u16MiuClient);
2356 u16RegVal3 |= (1<<u16MiuClient);
2357 }
2358 else if(u16MIUSelect[gop] == 3)
2359 {
2360 u16RegVal1 |= (1<<u16MiuClient);
2361 u16RegVal3 |= (1<<u16MiuClient);
2362 }
2363 bMIUSelect[gop] = FALSE;
2364 }
2365 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
2366 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
2367 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
2368 }
2369 }
2370 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_SC_MIU_SEL,u16RegVal1,0xFFFF);
2371 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
2372 return GOP_SUCCESS;
2373 }
2374 #endif
2375