Searched refs:REG_MISC_STATUS_0F (Results 1 – 12 of 12) sorted by relevance
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/include/ |
| H A D | regHDMITx.h | 338 #define REG_MISC_STATUS_0F 0x0FU macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/include/ |
| H A D | regHDMITx.h | 338 #define REG_MISC_STATUS_0F 0x0FU macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/include/ |
| H A D | regHDMITx.h | 338 #define REG_MISC_STATUS_0F 0x0FU macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/include/ |
| H A D | regHDMITx.h | 338 #define REG_MISC_STATUS_0F 0x0FU macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/include/ |
| H A D | regHDMITx.h | 348 #define REG_MISC_STATUS_0F 0x0FU macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/include/ |
| H A D | regHDMITx.h | 348 #define REG_MISC_STATUS_0F 0x0FU macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/ |
| H A D | halHDMITx.c | 677 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F, (u32Int>>16)); in MHal_HDMITx_Int_Clear()
703 reg_value |= (MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F)<<16); in MHal_HDMITx_Int_Status()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/ |
| H A D | halHDMITx.c | 700 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F, (u32Int>>16)); in MHal_HDMITx_Int_Clear()
726 reg_value |= (MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F)<<16); in MHal_HDMITx_Int_Status()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/ |
| H A D | halHDMITx.c | 726 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F, (u32Int>>16)); in MHal_HDMITx_Int_Clear()
752 reg_value |= (MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F)<<16); in MHal_HDMITx_Int_Status()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/ |
| H A D | halHDMITx.c | 714 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F, (u32Int>>16)); in MHal_HDMITx_Int_Clear()
740 reg_value |= (MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F)<<16); in MHal_HDMITx_Int_Status()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/ |
| H A D | halHDMITx.c | 848 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F, (u32Int>>16)); in MHal_HDMITx_Int_Clear()
874 reg_value |= (MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F)<<16); in MHal_HDMITx_Int_Status()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/ |
| H A D | halHDMITx.c | 903 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F, (u32Int>>16)); in MHal_HDMITx_Int_Clear()
929 reg_value |= (MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F)<<16); in MHal_HDMITx_Int_Status()
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