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Searched refs:REG_HDMI_2_CONFIG_1E (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/
H A DhalHDMITx.c2699 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, 0x0001, 0x0000); in MHal_HDMITx_SendPacket()
2709 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: c… in MHal_HDMITx_SendPacket()
2714 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (gbGeneralPktList[ucIn… in MHal_HDMITx_SendPacket()
2724 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: c… in MHal_HDMITx_SendPacket()
2729 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (HDMITX_PACKET_HDR_FCN… in MHal_HDMITx_SendPacket()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/
H A DhalHDMITx.c2682 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, 0x0001, 0x0000); in MHal_HDMITx_SendPacket()
2692 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: c… in MHal_HDMITx_SendPacket()
2697 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (gbGeneralPktList[ucIn… in MHal_HDMITx_SendPacket()
2707 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: c… in MHal_HDMITx_SendPacket()
2712 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (HDMITX_PACKET_HDR_FCN… in MHal_HDMITx_SendPacket()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/
H A DhalHDMITx.c2784 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, 0x0001, 0x0000); in MHal_HDMITx_SendPacket()
2794 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: c… in MHal_HDMITx_SendPacket()
2799 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (gbGeneralPktList[ucIn… in MHal_HDMITx_SendPacket()
2809 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: c… in MHal_HDMITx_SendPacket()
2814 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (HDMITX_PACKET_HDR_FCN… in MHal_HDMITx_SendPacket()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/
H A DhalHDMITx.c2746 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, 0x0001, 0x0000); in MHal_HDMITx_SendPacket()
2756 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: c… in MHal_HDMITx_SendPacket()
2761 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (gbGeneralPktList[ucIn… in MHal_HDMITx_SendPacket()
2771 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: c… in MHal_HDMITx_SendPacket()
2776 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (HDMITX_PACKET_HDR_FCN… in MHal_HDMITx_SendPacket()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/
H A DhalHDMITx.c3070 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, 0x0001, 0x0000); in MHal_HDMITx_SendPacket()
3080 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: c… in MHal_HDMITx_SendPacket()
3085 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (gbGeneralPktList[ucIn… in MHal_HDMITx_SendPacket()
3095 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: c… in MHal_HDMITx_SendPacket()
3100 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (HDMITX_PACKET_HDR_FCN… in MHal_HDMITx_SendPacket()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/
H A DhalHDMITx.c3185 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, 0x0001, 0x0000); in MHal_HDMITx_SendPacket()
3195 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: c… in MHal_HDMITx_SendPacket()
3200 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (gbGeneralPktList[ucIn… in MHal_HDMITx_SendPacket()
3210 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: c… in MHal_HDMITx_SendPacket()
3215 …MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (HDMITX_PACKET_HDR_FCN… in MHal_HDMITx_SendPacket()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/include/
H A DregHDMITx.h427 #define REG_HDMI_2_CONFIG_1E 0x1EU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/include/
H A DregHDMITx.h427 #define REG_HDMI_2_CONFIG_1E 0x1EU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/include/
H A DregHDMITx.h427 #define REG_HDMI_2_CONFIG_1E 0x1EU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/include/
H A DregHDMITx.h427 #define REG_HDMI_2_CONFIG_1E 0x1EU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/include/
H A DregHDMITx.h438 #define REG_HDMI_2_CONFIG_1E 0x1EU
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/include/
H A DregHDMITx.h438 #define REG_HDMI_2_CONFIG_1E 0x1EU