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Searched refs:REG_CKG_BT656 (Results 1 – 13 of 13) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A DhalPNL.c1427 …W2BYTEMSK(REG_CKG_BT656, CKG_BT656_CLK_LPLL, CKG_BT656_MASK); // select source tobe LPLL clock in MHal_PNL_Init_XC_Clk()
1428 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1429 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h219 #define REG_CKG_BT656 REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A DhalPNL.c1427 …W2BYTEMSK(REG_CKG_BT656, CKG_BT656_CLK_LPLL, CKG_BT656_MASK); // select source tobe LPLL clock in MHal_PNL_Init_XC_Clk()
1428 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1429 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h219 #define REG_CKG_BT656 REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A DhalPNL.c1767 …W2BYTEMSK(REG_CKG_BT656, CKG_BT656_CLK_LPLL, CKG_BT656_MASK); // select source tobe LPLL clock in MHal_PNL_Init_XC_Clk()
1768 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1769 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h229 #define REG_CKG_BT656 REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A DhalPNL.c1767 …W2BYTEMSK(REG_CKG_BT656, CKG_BT656_CLK_LPLL, CKG_BT656_MASK); // select source tobe LPLL clock in MHal_PNL_Init_XC_Clk()
1768 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1769 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h229 #define REG_CKG_BT656 REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.h261 #define REG_CKG_BT656 REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A DhalPNL.h232 #define REG_CKG_BT656 REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.h261 #define REG_CKG_BT656 REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A DhalPNL.h255 #define REG_CKG_BT656 REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A DhalPNL.h230 #define REG_CKG_BT656 REG_CLKGEN0_53_L macro