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Searched refs:REG_AE_CONFIG_05 (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/
H A DhalHDMITx.c476 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1086}, //[12]: CH status swap[7:0], [7]: enabl…
481 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disab…
486 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disab…
1062 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0001); //flush audio fifo in MHal_HDMITx_SetTMDSOnOff()
1064 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0000); in MHal_HDMITx_SetTMDSOnOff()
1542 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4|BIT5|BIT6, BIT5|BIT6); //[6:5… in MHal_HDMITx_SetAudioFrequency()
1546 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4, BIT4); //[4]=1'b1: 8 channels in MHal_HDMITx_SetAudioFrequency()
1576 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT9|BIT8, fmt << 8); in MHal_HDMITx_SetAudioSourceFormat()
1598 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, (MS_U16)bflag); in MHal_HDMITx_MuteAudioFIFO()
2802 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT0); // [7]: disable … in MHal_HDMITx_SendPacket()
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/
H A DhalHDMITx.c503 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1086}, //[12]: CH status swap[7:0], [7]: enabl…
508 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disab…
513 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disab…
1070 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0001); //flush audio fifo in MHal_HDMITx_SetTMDSOnOff()
1072 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0000); in MHal_HDMITx_SetTMDSOnOff()
1546 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4|BIT5|BIT6, BIT5|BIT6); //[6:5… in MHal_HDMITx_SetAudioFrequency()
1550 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4, BIT4); //[4]=1'b1: 8 channels in MHal_HDMITx_SetAudioFrequency()
1580 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT9|BIT8, fmt << 8); in MHal_HDMITx_SetAudioSourceFormat()
1602 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, (MS_U16)bflag); in MHal_HDMITx_MuteAudioFIFO()
2785 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT0); // [7]: disable … in MHal_HDMITx_SendPacket()
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/
H A DhalHDMITx.c523 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1086}, //[12]: CH status swap[7:0], [7]: enabl…
528 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disab…
533 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disab…
1110 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0001); //flush audio fifo in MHal_HDMITx_SetTMDSOnOff()
1112 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0000); in MHal_HDMITx_SetTMDSOnOff()
1621 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4|BIT5|BIT6, BIT5|BIT6); //[6:5… in MHal_HDMITx_SetAudioFrequency()
1625 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4, BIT4); //[4]=1'b1: 8 channels in MHal_HDMITx_SetAudioFrequency()
1655 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT9|BIT8, fmt << 8); in MHal_HDMITx_SetAudioSourceFormat()
1677 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, (MS_U16)bflag); in MHal_HDMITx_MuteAudioFIFO()
2887 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT0); // [7]: disable … in MHal_HDMITx_SendPacket()
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/
H A DhalHDMITx.c511 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1086}, //[12]: CH status swap[7:0], [7]: enabl…
516 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disab…
521 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disab…
1098 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0001); //flush audio fifo in MHal_HDMITx_SetTMDSOnOff()
1100 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0000); in MHal_HDMITx_SetTMDSOnOff()
1558 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4|BIT5|BIT6, BIT5|BIT6); //[6:5… in MHal_HDMITx_SetAudioFrequency()
1562 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4, BIT4); //[4]=1'b1: 8 channels in MHal_HDMITx_SetAudioFrequency()
1592 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT9|BIT8, fmt << 8); in MHal_HDMITx_SetAudioSourceFormat()
1614 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, (MS_U16)bflag); in MHal_HDMITx_MuteAudioFIFO()
2849 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT0); // [7]: disable … in MHal_HDMITx_SendPacket()
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/
H A DhalHDMITx.c652 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1086}, //[12]: CH status swap[7:0], [7]: enabl…
657 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disab…
662 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disab…
1239 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0001); //flush audio fifo in MHal_HDMITx_SetTMDSOnOff()
1241 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0000); in MHal_HDMITx_SetTMDSOnOff()
1670 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4|BIT5|BIT6, BIT5|BIT6); //[6:5… in MHal_HDMITx_SetAudioFrequency()
1674 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4, BIT4); //[4]=1'b1: 8 channels in MHal_HDMITx_SetAudioFrequency()
1704 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT9|BIT8, fmt << 8); in MHal_HDMITx_SetAudioSourceFormat()
1726 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, (MS_U16)bflag); in MHal_HDMITx_MuteAudioFIFO()
3173 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT0); // [7]: disable … in MHal_HDMITx_SendPacket()
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/
H A DhalHDMITx.c700 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1086}, //[12]: CH status swap[7:0], [7]: enabl…
705 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disab…
710 …{HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disab…
1294 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0001); //flush audio fifo in MHal_HDMITx_SetTMDSOnOff()
1296 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0000); in MHal_HDMITx_SetTMDSOnOff()
1756 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4|BIT5|BIT6, BIT5|BIT6); //[6:5… in MHal_HDMITx_SetAudioFrequency()
1760 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4, BIT4); //[4]=1'b1: 8 channels in MHal_HDMITx_SetAudioFrequency()
1790 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT9|BIT8, fmt << 8); in MHal_HDMITx_SetAudioSourceFormat()
1812 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, (MS_U16)bflag); in MHal_HDMITx_MuteAudioFIFO()
3288 …MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT0); // [7]: disable … in MHal_HDMITx_SendPacket()
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/include/
H A DregHDMITx.h312 #define REG_AE_CONFIG_05 0x05U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/include/
H A DregHDMITx.h312 #define REG_AE_CONFIG_05 0x05U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/include/
H A DregHDMITx.h312 #define REG_AE_CONFIG_05 0x05U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/include/
H A DregHDMITx.h312 #define REG_AE_CONFIG_05 0x05U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/include/
H A DregHDMITx.h322 #define REG_AE_CONFIG_05 0x05U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/include/
H A DregHDMITx.h322 #define REG_AE_CONFIG_05 0x05U macro