| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/ |
| H A D | halTSP.c | 136 #define REG16_SET(reg, value) REG16_W(reg, _SET_(REG16_R(reg), value)) macro
335 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE); in HAL_TSP_HwPatch()
336 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_HwPatch()
340 …REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WST… in HAL_TSP_HwPatch()
349 REG16_SET(&_RegCtrl->reg15b4, TSP_PVR_PID_BYPASS|TSP_PVR_PID_BYPASS2); in HAL_TSP_HwPatch()
350 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PID_BYPASS3_REC); in HAL_TSP_HwPatch()
351 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PID_BYPASS4_REC); in HAL_TSP_HwPatch()
354 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD); in HAL_TSP_HwPatch()
356 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_TSP_HwPatch()
357 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD); in HAL_TSP_HwPatch()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/ |
| H A D | halTSP.c | 118 #define REG16_SET(reg, value) REG16_W(reg, _SET_(REG16_R(reg), value)) macro
258 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE); in HAL_TSP_HwPatch()
259 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_HwPatch()
263 …REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WST… in HAL_TSP_HwPatch()
272 REG16_SET(&_RegCtrl->reg15b4, TSP_PVR_PID_BYPASS|TSP_PVR_PID_BYPASS2); in HAL_TSP_HwPatch()
273 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PID_BYPASS3_REC); in HAL_TSP_HwPatch()
274 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PID_BYPASS4_REC); in HAL_TSP_HwPatch()
277 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD); in HAL_TSP_HwPatch()
279 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_TSP_HwPatch()
280 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD); in HAL_TSP_HwPatch()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/ |
| H A D | halTSP.c | 139 #define REG16_SET(reg, value) REG16_W(reg, _SET_(REG16_R(reg), value)) macro
337 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE); in HAL_TSP_HwPatch()
338 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_HwPatch()
342 …REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WST… in HAL_TSP_HwPatch()
351 REG16_SET(&_RegCtrl->reg15b4, TSP_PVR_PID_BYPASS|TSP_PVR_PID_BYPASS2); in HAL_TSP_HwPatch()
352 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PID_BYPASS3_REC); in HAL_TSP_HwPatch()
353 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PID_BYPASS4_REC); in HAL_TSP_HwPatch()
356 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD); in HAL_TSP_HwPatch()
358 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_TSP_HwPatch()
359 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD); in HAL_TSP_HwPatch()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/ |
| H A D | halTSP.c | 111 #define REG16_SET(reg, value) REG16_W(reg, _SET_(REG16_R(reg), value)) macro
250 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE); in HAL_TSP_HwPatch()
251 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_HwPatch()
255 …REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WST… in HAL_TSP_HwPatch()
264 REG16_SET(&_RegCtrl->reg15b4, TSP_PVR_PID_BYPASS|TSP_PVR_PID_BYPASS2); in HAL_TSP_HwPatch()
265 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PID_BYPASS3_REC); in HAL_TSP_HwPatch()
266 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PID_BYPASS4_REC); in HAL_TSP_HwPatch()
268 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT); in HAL_TSP_HwPatch()
270 …REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ2PINGPONG_EN | TSP_RM_PKT_DEMUX_PIPE /*| TSP_PVR1_ALIGN_EN… in HAL_TSP_HwPatch()
273 …REG16_SET(&_RegCtrl->reg160C, TSP_DOUBLE_BUF_DESC/*| TSP_VQTX0_BLOCK_DIS|TSP_VQTX2_BLOCK_DIS|TSP_V… in HAL_TSP_HwPatch()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/ |
| H A D | halTSP.c | 119 #define REG16_SET(reg, value) REG16_W(reg, _SET_(REG16_R(reg), value)) macro
273 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE); in HAL_TSP_HwPatch()
274 REG16_SET(&_RegOtherCtrl->CFG_OTHER_16, CFG_OHTER_16_REG_PREVENT_SRAM_COLLISION); in HAL_TSP_HwPatch()
278 …REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WST… in HAL_TSP_HwPatch()
294 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_RECORD_TS); in HAL_TSP_HwPatch()
300 … REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_0D, CFG_PVR_0D_REG_PVR_WRITE_POINTER_TO_NEXT_ADDRESS_EN); in HAL_TSP_HwPatch()
303 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_SKIP_PVR_RUSH_DATA); in HAL_TSP_HwPatch()
309 REG16_SET(&_RegPcrCtrl[u8Idx].CFG_PCR_00, CFG_PCR_00_REG_SKIP_PVR_RUSH_DATA); in HAL_TSP_HwPatch()
314 …REG16_SET(&_RegAudioCtrl[u8Idx].CFG_AV_00, (CFG_AV_00_REG_DUP_PKT_SKIP | CFG_AV_00_REG_PUSI_THREE_… in HAL_TSP_HwPatch()
319 …REG16_SET(&_RegVideoCtrl[u8Idx].CFG_AV_00, (CFG_AV_00_REG_DUP_PKT_SKIP | CFG_AV_00_REG_PUSI_THREE_… in HAL_TSP_HwPatch()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/multi_pvr/ |
| H A D | halMultiPVR.c | 148 #define REG16_SET(reg, value) REG16_W(reg, _SET_(REG16_R(reg), value)) macro
184 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_40, CFG_MULTI_PVR_40_REG_ACPU_ACTIVE); in _HAL_MultiPVR_IdrW()
200 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_40, CFG_MULTI_PVR_40_REG_ACPU_ACTIVE); in _HAL_MultiPVR_IdrR()
271 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_RECORD_TS); in HAL_MultiPVR_Init()
277 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_00, CFG_MULTI_PVR_00_REG_PVR_STR2MI_EN); in HAL_MultiPVR_Init()
294 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_DIS_NULL_PKT); in HAL_MultiPVR_Exit()
301 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_00, CFG_MULTI_PVR_00_REG_PVR_DMA_FLUSH_EN); in HAL_MultiPVR_FlushData()
311 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_MASK_SCR_PVR_EN); in HAL_MultiPVR_Skip_Scrmb()
325 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_PVR_BLOCK_DISABLE); in HAL_MultiPVR_Block_Dis()
414 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_00, CFG_MULTI_PVR_00_REG_PVR_STR2MI_PAUSE); in HAL_MultiPVR_Pause()
[all …]
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/dscmb/ |
| H A D | halDSCMB.c | 133 #define REG16_SET(reg, value); REG16_W(reg, _SET_(REG16_R(reg), value)); macro
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/dscmb/ |
| H A D | halDSCMB.c | 133 #define REG16_SET(reg, value); REG16_W(reg, _SET_(REG16_R(reg), value)); macro
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/dscmb/ |
| H A D | halDSCMB.c | 133 #define REG16_SET(reg, value); REG16_W(reg, _SET_(REG16_R(reg), value)); macro
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/dscmb/ |
| H A D | halDSCMB.c | 133 #define REG16_SET(reg, value); REG16_W(reg, _SET_(REG16_R(reg), value)); macro
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/dscmb/ |
| H A D | halDSCMB.c | 133 #define REG16_SET(reg, value); REG16_W(reg, _SET_(REG16_R(reg), value)); macro
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