Lines Matching refs:REG16_SET
139 #define REG16_SET(reg, value) REG16_W(reg, _SET_(REG16_R(reg), value)) macro
337 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE); in HAL_TSP_HwPatch()
338 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_HwPatch()
342 …REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WST… in HAL_TSP_HwPatch()
351 REG16_SET(&_RegCtrl->reg15b4, TSP_PVR_PID_BYPASS|TSP_PVR_PID_BYPASS2); in HAL_TSP_HwPatch()
352 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PID_BYPASS3_REC); in HAL_TSP_HwPatch()
353 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PID_BYPASS4_REC); in HAL_TSP_HwPatch()
356 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD); in HAL_TSP_HwPatch()
358 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_TSP_HwPatch()
359 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD); in HAL_TSP_HwPatch()
361 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT); in HAL_TSP_HwPatch()
364 …REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ2PINGPONG_EN | TSP_RM_PKT_DEMUX_PIPE /*| TSP_PVR1_ALIGN_EN… in HAL_TSP_HwPatch()
367 …REG16_SET(&_RegCtrl->reg160C, TSP_DOUBLE_BUF_DESC/*| TSP_VQTX0_BLOCK_DIS|TSP_VQTX2_BLOCK_DIS|TSP_V… in HAL_TSP_HwPatch()
368 REG16_SET(&_RegCtrl->reg160E, TSP_RM_DMA_GLITCH); in HAL_TSP_HwPatch()
370 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PUSI_3BYTE_MODE); //Enable audio 3 byte mode in HAL_TSP_HwPatch()
372 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_HwPatch()
375 REG16_SET(&_RegCtrl->PVRConfig, TSP_MATCH_PID_LD | TSP_REC_NULL); in HAL_TSP_HwPatch()
376 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BLK_AD_SCMBTIS_TSP); in HAL_TSP_HwPatch()
383 REG16_SET(&_RegCtrl3->CFG3_16, CFG3_16_FIXED_DMA_RSTART_OTP_ONEWAY_LOAD_FW); in HAL_TSP_HwPatch()
386 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_DATA_CHK_2T); in HAL_TSP_HwPatch()
391 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_FIX_FILTER_NULL_PKT); in HAL_TSP_HwPatch()
395 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_FIX_192_TIMER_0_EN); in HAL_TSP_HwPatch()
399 REG16_SET(&_RegCtrl6->CFG6_2A, FIXED_TIMESTAMP_RING_BACK_EN | FIXED_LPCR_RING_BACK_EN); in HAL_TSP_HwPatch()
402 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_SYNC_RISING_DETECT | TSP_VALID_FALLING_DETECT); in HAL_TSP_HwPatch()
406 REG16_SET(&_RegCtrl6->CFG6_2A, FIXED_VQ_MIU_REG_FLUSH); in HAL_TSP_HwPatch()
451 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Reset()
452 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
453 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Reset()
454 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Reset()
455 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
460 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
478 REG16_SET(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET); in HAL_TSP_Path_Reset()
479 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0); in HAL_TSP_Path_Reset()
480 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0); in HAL_TSP_Path_Reset()
491 REG16_SET(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1); in HAL_TSP_Path_Reset()
492 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1); in HAL_TSP_Path_Reset()
493 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1); in HAL_TSP_Path_Reset()
504 REG16_SET(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2); in HAL_TSP_Path_Reset()
505 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2); in HAL_TSP_Path_Reset()
506 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2); in HAL_TSP_Path_Reset()
517 REG16_SET(&_RegCtrl2->CFG_0A,CFG_0A_RST_TS_FIN3); in HAL_TSP_Path_Reset()
518 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT3); in HAL_TSP_Path_Reset()
519 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF3 | CFG_12_REG_REST_PDBF3); in HAL_TSP_Path_Reset()
635 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_Power()
638 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE);//TSP in HAL_TSP_Power()
723 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_CPU()
739 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_ResetCPU()
773 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START); in HAL_TSP_LoadFW()
837 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0); in HAL_TSP_PktBuf_Reset()
840 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1); in HAL_TSP_PktBuf_Reset()
843 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2); in HAL_TSP_PktBuf_Reset()
846 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF3); in HAL_TSP_PktBuf_Reset()
881 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0); in HAL_TSP_RecvBuf_Reset()
884 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1); in HAL_TSP_RecvBuf_Reset()
887 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2); in HAL_TSP_RecvBuf_Reset()
890 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF3); in HAL_TSP_RecvBuf_Reset()
949 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE); in HAL_TSP_TSIF_LiveEn()
952 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE); in HAL_TSP_TSIF_LiveEn()
958 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_IF3_EN); in HAL_TSP_TSIF_LiveEn()
1630 …REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); // for wishbone DMA (load firm… in HAL_TSP_TSIF_FileEn()
1631 … REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL); //Tsif0 output is live TS in HAL_TSP_TSIF_FileEn()
1632 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN); //filein enable in HAL_TSP_TSIF_FileEn()
1635 …REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1); // for wishbone DMA (load firm… in HAL_TSP_TSIF_FileEn()
1636 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1); in HAL_TSP_TSIF_FileEn()
1637 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1); in HAL_TSP_TSIF_FileEn()
1638 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN); //filein enable in HAL_TSP_TSIF_FileEn()
1641 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2); in HAL_TSP_TSIF_FileEn()
1642 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2); in HAL_TSP_TSIF_FileEn()
1643 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2); in HAL_TSP_TSIF_FileEn()
1644 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2); in HAL_TSP_TSIF_FileEn()
1647 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TSP_FILE_SEGMENT3); in HAL_TSP_TSIF_FileEn()
1648 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_SEGMENT_TSIF3); in HAL_TSP_TSIF_FileEn()
1649 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA_PORT_SEL3); in HAL_TSP_TSIF_FileEn()
1650 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_IN_TSIF3); in HAL_TSP_TSIF_FileEn()
1698 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP); in HAL_TSP_TSIF_BitSwap()
1701 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP); in HAL_TSP_TSIF_BitSwap()
1707 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA3_SWAP); in HAL_TSP_TSIF_BitSwap()
1744 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1747 REG16_SET(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1753 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_EXT_SYNC_SEL3); in HAL_TSP_TSIF_ExtSync()
1791 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP); in HAL_TSP_Filein_Bypass()
1794 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP1); in HAL_TSP_Filein_Bypass()
1797 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP2); in HAL_TSP_Filein_Bypass()
1800 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP3); in HAL_TSP_Filein_Bypass()
1838 REG16_SET(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL); in HAL_TSP_TSIF_Parl()
1841 REG16_SET(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL); in HAL_TSP_TSIF_Parl()
1847 REG16_SET(&(_RegCtrl2->CFG_0B), CFG_0B_P_SEL3); in HAL_TSP_TSIF_Parl()
1929 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS0); in HAL_TSP_TSIF_3Wire()
1932 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS1); in HAL_TSP_TSIF_3Wire()
1935 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS2); in HAL_TSP_TSIF_3Wire()
1938 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS3); in HAL_TSP_TSIF_3Wire()
1971 …REG16_SET(&_RegCtrl3->CFG3_0C, ((1 << pktDmxId) << CFG3_0C_PKTDMX_CC_DROP_SHIFT) & CFG3_0C_PKTDMX_… in HAL_TSP_PktDmx_CCDrop()
2007 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V_EN); in HAL_TSP_TRACE_MARK_En()
2010 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V3D_EN); in HAL_TSP_TRACE_MARK_En()
2013 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_A_EN); in HAL_TSP_TRACE_MARK_En()
2016 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_AB_EN); in HAL_TSP_TRACE_MARK_En()
2026 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V_EN); in HAL_TSP_TRACE_MARK_En()
2029 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V3D_EN); in HAL_TSP_TRACE_MARK_En()
2032 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_A_EN); in HAL_TSP_TRACE_MARK_En()
2035 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_AB_EN); in HAL_TSP_TRACE_MARK_En()
2045 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V_EN); in HAL_TSP_TRACE_MARK_En()
2048 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V3D_EN); in HAL_TSP_TRACE_MARK_En()
2051 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_A_EN); in HAL_TSP_TRACE_MARK_En()
2054 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_AB_EN); in HAL_TSP_TRACE_MARK_En()
2064 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_V_EN); in HAL_TSP_TRACE_MARK_En()
2067 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_V3D_EN); in HAL_TSP_TRACE_MARK_En()
2070 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_A_EN); in HAL_TSP_TRACE_MARK_En()
2073 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_AB_EN); in HAL_TSP_TRACE_MARK_En()
2177 REG16_SET(&_RegCtrl->reg15b4, TSP_BD_AUD_EN); in HAL_TSP_BD_AUD_En()
2180 REG16_SET(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN); in HAL_TSP_BD_AUD_En()
2249 REG16_SET(&_RegCtrl3->CFG3_36, u16value); in HAL_TSP_Filein_PktSize()
2253 REG16_SET(&_RegCtrl3->CFG3_36, u16value); in HAL_TSP_Filein_PktSize()
2259 REG16_SET(&_RegCtrl4->CFG4_54, u16value); in HAL_TSP_Filein_PktSize()
2263 REG16_SET(&_RegCtrl4->CFG4_54, u16value); in HAL_TSP_Filein_PktSize()
2274 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_ALT_TS_SIZE); in HAL_TSP_Filein_PktSize()
2338 REG16_SET(&_RegCtrl->TsDma_Ctrl, TSP_TSDMA_CTRL_START); in HAL_TSP_Filein_Start()
2341 REG16_SET(&_RegCtrl2->CFG_34, CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START); in HAL_TSP_Filein_Start()
2344 REG16_SET(&_RegCtrl2->CFG_39, CFG_39_FILEIN_CTRL_TSIF2_START); in HAL_TSP_Filein_Start()
2347 REG16_SET(&_RegCtrl2->CFG_3E, CFG_3E_FILEIN_CTRL_TSIF3_START); in HAL_TSP_Filein_Start()
2359 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE); in HAL_TSP_File_Pause()
2362 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF1_FILE_PAUSE); in HAL_TSP_File_Pause()
2365 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF2_FILE_PAUSE); in HAL_TSP_File_Pause()
2368 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF3_FILE_PAUSE); in HAL_TSP_File_Pause()
2401 REG16_SET(&_RegCtrl->TsDma_Ctrl, (TSP_TSDMA_INIT_TRUST | TSP_TSDMA_CTRL_START)); in HAL_TSP_Filein_Init_Trust_Start()
2404 …REG16_SET(&_RegCtrl2->CFG_34, (CFG_34_REG_TSP_FILEIN_INIT_TRUST_TSIF1 | CFG_34_REG_TSP_FILEIN_CTRL… in HAL_TSP_Filein_Init_Trust_Start()
2407 … REG16_SET(&_RegCtrl2->CFG_39, (CFG_39_FILEIN_INIT_TRUST_TSIF2 | CFG_39_FILEIN_CTRL_TSIF2_START)); in HAL_TSP_Filein_Init_Trust_Start()
2410 … REG16_SET(&_RegCtrl2->CFG_3E, (CFG_3E_FILEIN_INIT_TRUST_TSIF3 | CFG_3E_FILEIN_CTRL_TSIF3_START)); in HAL_TSP_Filein_Init_Trust_Start()
2424 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0); in HAL_TSP_Filein_Abort()
2427 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1); in HAL_TSP_Filein_Abort()
2430 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2); in HAL_TSP_Filein_Abort()
2433 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF3); in HAL_TSP_Filein_Abort()
2468 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Filein_CmdQRst()
2471 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Filein_CmdQRst()
2474 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Filein_CmdQRst()
2477 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Filein_CmdQRst()
2565 REG16_SET(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE); in HAL_TSP_Filein_ByteDelay()
2569 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1); in HAL_TSP_Filein_ByteDelay()
2573 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2); in HAL_TSP_Filein_ByteDelay()
2577 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TIMER_EN3); in HAL_TSP_Filein_ByteDelay()
2713 REG16_SET(&_RegCtrl->reg160C, TSP_FILEIN192_EN); in HAL_TSP_Filein_PacketMode()
2716 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1); in HAL_TSP_Filein_PacketMode()
2719 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2); in HAL_TSP_Filein_PacketMode()
2722 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_EN3); in HAL_TSP_Filein_PacketMode()
2777 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN); in HAL_TSP_Filein_BlockTimeStamp()
2780 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1); in HAL_TSP_Filein_BlockTimeStamp()
2783 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2); in HAL_TSP_Filein_BlockTimeStamp()
2786 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_BLK_DISABLE3); in HAL_TSP_Filein_BlockTimeStamp()
2799 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_0); in _HAL_TSP_FILEIN_ResetPktTimeStamp()
2804 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_1); in _HAL_TSP_FILEIN_ResetPktTimeStamp()
2809 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_2); in _HAL_TSP_FILEIN_ResetPktTimeStamp()
2814 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_3); in _HAL_TSP_FILEIN_ResetPktTimeStamp()
2828 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_WLD); in HAL_TSP_Filein_SetTimeStamp()
2833 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1); in HAL_TSP_Filein_SetTimeStamp()
2838 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2); in HAL_TSP_Filein_SetTimeStamp()
2843 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_LPCR2_WLD3); in HAL_TSP_Filein_SetTimeStamp()
2861 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF0_C27M); in HAL_TSP_Filein_SetTimeStampClk()
2871 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF1_C27M); in HAL_TSP_Filein_SetTimeStampClk()
2881 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF2_C27M); in HAL_TSP_Filein_SetTimeStampClk()
2891 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF3_C27M); in HAL_TSP_Filein_SetTimeStampClk()
2911 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_RLD); in HAL_TSP_Filein_GetTimeStamp()
2916 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1); in HAL_TSP_Filein_GetTimeStamp()
2921 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2); in HAL_TSP_Filein_GetTimeStamp()
2926 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_LPCR2_LOAD_TSIF3); in HAL_TSP_Filein_GetTimeStamp()
2982 REG16_SET(&_RegCtrl3->CFG3_53, CFG3_53_WB_FSM_RESET); in HAL_TSP_Filein_WbFsmRst()
2985 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1); in HAL_TSP_Filein_WbFsmRst()
2988 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2); in HAL_TSP_Filein_WbFsmRst()
2991 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF3); in HAL_TSP_Filein_WbFsmRst()
3152 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SEC_DMA_BURST_EN); in HAL_TSP_SecFlt_BurstLen()
3428 REG16_SET(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN); in HAL_TSP_PcrFlt_Enable()
3438 REG16_SET(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN); in HAL_TSP_PcrFlt_Enable()
3558 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ); in HAL_TSP_PcrFlt_GetPcr()
3564 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ); in HAL_TSP_PcrFlt_GetPcr()
3580 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET); in HAL_TSP_PcrFlt_Reset()
3584 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET); in HAL_TSP_PcrFlt_Reset()
3722 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_STC64_Mode_En()
3753 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC64_Get()
3759 REG16_SET(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld); in HAL_TSP_STC64_Get()
3777 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC33_CmdQGet()
3851 REG16_SET(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN); in HAL_TSP_FIFO_Connect()
3908 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS); in HAL_TSP_Flt_Bypass()
3911 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS); in HAL_TSP_Flt_Bypass()
3914 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_B_BYPASS); in HAL_TSP_Flt_Bypass()
3917 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_VPID_3D_BYPASS); in HAL_TSP_Flt_Bypass()
3920 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_C_BYPASS); in HAL_TSP_Flt_Bypass()
3923 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_D_BYPASS); in HAL_TSP_Flt_Bypass()
3975 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN); in HAL_TSP_FIFO_Bypass()
3978 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
3981 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN); in HAL_TSP_FIFO_Bypass()
3984 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN); in HAL_TSP_FIFO_Bypass()
3987 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN); in HAL_TSP_FIFO_Bypass()
3990 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN); in HAL_TSP_FIFO_Bypass()
4058 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO); in HAL_TSP_FIFO_Reset()
4061 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D); in HAL_TSP_FIFO_Reset()
4065 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO); in HAL_TSP_FIFO_Reset()
4068 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO2); in HAL_TSP_FIFO_Reset()
4071 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO3); in HAL_TSP_FIFO_Reset()
4074 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_RESET_AFIFO4); in HAL_TSP_FIFO_Reset()
4118 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V_EN); in HAL_TSP_FIFO_Skip_Scrmb()
4121 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V3D_EN); in HAL_TSP_FIFO_Skip_Scrmb()
4124 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_A_EN); in HAL_TSP_FIFO_Skip_Scrmb()
4127 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AB_EN); in HAL_TSP_FIFO_Skip_Scrmb()
4130 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AC_EN); in HAL_TSP_FIFO_Skip_Scrmb()
4133 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AD_EN); in HAL_TSP_FIFO_Skip_Scrmb()
4447 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4450 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4453 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4456 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX3_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4490 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN); in HAL_TSP_VQ_Enable()
4504 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET); in HAL_TSP_VQ_Reset()
4507 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET); in HAL_TSP_VQ_Reset()
4510 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET); in HAL_TSP_VQ_Reset()
4513 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_RESET); in HAL_TSP_VQ_Reset()
4548 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
4551 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
4554 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
4557 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
4592 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT); in HAL_TSP_VQ_OverflowInt_Clr()
4595 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
4598 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
4601 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
4635 REG16_SET(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG); in HAL_PVR_Init()
4647 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_REG_PINGPONG_EN); in HAL_PVR_Init()
4652 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_REG_PINGPONG_EN); in HAL_PVR_Init()
4669 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
4688 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Exit()
4697 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR); in HAL_PVR_Exit()
4720 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
4724 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE); in HAL_PVR_Start()
4736 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Start()
4740 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_EN); in HAL_PVR_Start()
4744 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR); in HAL_PVR_Start()
4748 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_EN); in HAL_PVR_Start()
4793 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
4799 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_PAUSE); in HAL_PVR_Pause()
4802 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_PAUSE); in HAL_PVR_Pause()
4837 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS); in HAL_PVR_RecPid()
4841 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2); in HAL_PVR_RecPid()
4845 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PID_BYPASS3_REC); in HAL_PVR_RecPid()
4849 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PID_BYPASS4_REC); in HAL_PVR_RecPid()
4862 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN); in HAL_PVR_RecPid()
4866 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN); in HAL_PVR_RecPid()
4870 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_REC_ALL3); in HAL_PVR_RecPid()
4874 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_REC_ALL4); in HAL_PVR_RecPid()
4886 REG16_SET(&(_RegCtrl->PVRConfig), TSP_REC_NULL); in HAL_PVR_RecNull()
5410 REG16_SET(&_RegCtrl->reg160C, TSP_RECORD192_EN); in HAL_PVR_SetStrPacketMode()
5416 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5419 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5457 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5472 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5479 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5492 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5506 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5513 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5529 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0); in HAL_PVR_SetPVRTimeStamp_Stream()
5536 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1); in HAL_PVR_SetPVRTimeStamp_Stream()
5543 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD2); in HAL_PVR_SetPVRTimeStamp_Stream()
5550 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD3); in HAL_PVR_SetPVRTimeStamp_Stream()
5568 REG16_SET(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5574 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5577 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5610 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR_DATA); in HAL_PVR_FlushData()
5614 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR1_DATA); in HAL_PVR_FlushData()
5618 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR2_DATA); in HAL_PVR_FlushData()
5622 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR3_DATA); in HAL_PVR_FlushData()
5637 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN); in HAL_PVR_Skip_Scrmb()
5640 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN); in HAL_PVR_Skip_Scrmb()
5643 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR3_EN); in HAL_PVR_Skip_Scrmb()
5646 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR4_EN); in HAL_PVR_Skip_Scrmb()
5688 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_BLOCK_DIS); in HAL_PVR_Block_Dis()
5691 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_BLOCK_DIS); in HAL_PVR_Block_Dis()
5750 REG16_SET((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng)); in HAL_PVR_TimeStamp_Sel()
5785 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1); in HAL_PVR_PauseTime_En()
5788 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL2); in HAL_PVR_PauseTime_En()
5791 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL3); in HAL_PVR_PauseTime_En()
5794 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL4); in HAL_PVR_PauseTime_En()
5827 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2)); in HAL_PVR_TimeStamp_Stream_En()
6040 REG16_SET(&_RegCtrl->DBG_SEL, ((u16Sel << TSP_DBG_SEL_SHIFT) & TSP_DBG_SEL_MASK)); in HAL_TSP_GetDBGStatus()
6058 REG16_SET(&_RegCtrl->HwInt_Stat, TSP_INT_EN_MASK & u32Mask); in HAL_TSP_INT_Enable()
6071 …REG16_SET(&_RegCtrl->SwInt_Stat1_L, (TSP_HWINT2_EN_MASK & (u32Mask >> 8)) | TSP_HWINT2_STATUS_MASK… in HAL_TSP_INT_Enable()
6141 …REG16_SET(&_RegCtrl3->CFG3_52, CFG3_52_SPD_TSIF0_BYPASS | CFG3_52_SPD_TSIF1_BYPASS | CFG3_52_SPD_T… in HAL_TSP_SPD_Bypass_En()
6156 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_CTR_MODE_SPD_FILEIN); //set CTR mode enable in HAL_TSP_FileIn_SPDConfig()
6162 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_LOAD_INIT_CNT_SPD); //load counter IV in HAL_TSP_FileIn_SPDConfig()
6176 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY0); in HAL_TSP_FileIn_SPDConfig()
6178 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF0_SPD_RESET); //TSIF SPD reset in HAL_TSP_FileIn_SPDConfig()
6200 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY1); in HAL_TSP_FileIn_SPDConfig()
6202 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF1_SPD_RESET); //TSIF SPD reset in HAL_TSP_FileIn_SPDConfig()
6224 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY2); in HAL_TSP_FileIn_SPDConfig()
6226 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF2_SPD_RESET); //TSIF SPD reset in HAL_TSP_FileIn_SPDConfig()
6248 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY3); in HAL_TSP_FileIn_SPDConfig()
6250 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF3_SPD_RESET); //TSIF SPD reset in HAL_TSP_FileIn_SPDConfig()
6404 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT); in HAL_TSP_PktDmx_RmDupAVPkt()
6419 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
6422 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
6451 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0); in HAL_TSP_TEI_SKIP()
6454 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1); in HAL_TSP_TEI_SKIP()
6460 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID3); in HAL_TSP_TEI_SKIP()
6494 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR); in HAL_TSP_DisPKTCnt_Clear()
6498 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_DisPKTCnt_Clear()
6502 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR); in HAL_TSP_DisPKTCnt_Clear()
6506 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR); in HAL_TSP_DisPKTCnt_Clear()
6510 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADC_CLR); in HAL_TSP_DisPKTCnt_Clear()
6514 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADD_CLR); in HAL_TSP_DisPKTCnt_Clear()
6542 REG16_SET(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN); in HAL_TSP_OR_Address_Protect_En()
6563 REG16_SET(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN); in HAL_TSP_SEC_Address_Protect_En()
6599 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR1_DMAW_PROTECT_EN); in HAL_TSP_PVR_Address_Protect_En()
6602 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR2_DMAW_PROTECT_EN); in HAL_TSP_PVR_Address_Protect_En()
6605 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR3_DMAW_PROTECT_EN); in HAL_TSP_PVR_Address_Protect_En()
6608 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR4_DMAW_PROTECT_EN); in HAL_TSP_PVR_Address_Protect_En()
6672 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN0_DMAR_PROTECT_EN); in HAL_TSP_FILEIN_Address_Protect_En()
6675 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN1_DMAR_PROTECT_EN); in HAL_TSP_FILEIN_Address_Protect_En()
6678 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN2_DMAR_PROTECT_EN); in HAL_TSP_FILEIN_Address_Protect_En()
6681 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN3_DMAR_PROTECT_EN); in HAL_TSP_FILEIN_Address_Protect_En()
6745 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_MMFI0_DMAR_PROTECT_EN); in HAL_TSP_MMFI_Address_Protect_En()
6748 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_MMFI1_DMAR_PROTECT_EN); in HAL_TSP_MMFI_Address_Protect_En()
6905 case 0: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN1); in HAL_TSP_PVR_SPSConfig()
6915 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY1); in HAL_TSP_PVR_SPSConfig()
6917 case 1: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN2); in HAL_TSP_PVR_SPSConfig()
6937 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY2); in HAL_TSP_PVR_SPSConfig()
6939 case 2: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN3); in HAL_TSP_PVR_SPSConfig()
6959 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY3); in HAL_TSP_PVR_SPSConfig()
6961 case 3: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN4); in HAL_TSP_PVR_SPSConfig()
6981 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY4); in HAL_TSP_PVR_SPSConfig()
6990 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1); //set CTR mode in HAL_TSP_PVR_SPSConfig()
6996 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1); //load counter IV in HAL_TSP_PVR_SPSConfig()
7353 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_0_LOAD); in HAL_TSP_Debug_LockPktCnt_Load()
7356 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_1_LOAD); in HAL_TSP_Debug_LockPktCnt_Load()
7359 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_2_LOAD); in HAL_TSP_Debug_LockPktCnt_Load()
7362 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_3_LOAD); in HAL_TSP_Debug_LockPktCnt_Load()
7401 REG16_SET(&_RegCtrl3->CFG3_37,HW4_CFG37_NON_188_CNT_MODE); in HAL_TSP_Debug_LockPktCnt_Get()
7412 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_0_CLR); in HAL_TSP_Debug_LockPktCnt_Clear()
7416 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_1_CLR); in HAL_TSP_Debug_LockPktCnt_Clear()
7420 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_2_CLR); in HAL_TSP_Debug_LockPktCnt_Clear()
7424 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_3_CLR); in HAL_TSP_Debug_LockPktCnt_Clear()
7523 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_V_PKT_CNT_LOAD); in HAL_TSP_Debug_AvPktCnt_Load()
7526 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_V3D_PKT_CNT_LOAD); in HAL_TSP_Debug_AvPktCnt_Load()
7529 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_A_PKT_CNT_LOAD); in HAL_TSP_Debug_AvPktCnt_Load()
7532 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_AD_PKT_CNT_LOAD); in HAL_TSP_Debug_AvPktCnt_Load()
7535 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_ADC_PKT_CNT_LOAD); in HAL_TSP_Debug_AvPktCnt_Load()
7538 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_ADD_PKT_CNT_LOAD); in HAL_TSP_Debug_AvPktCnt_Load()
7585 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL); in HAL_TSP_Debug_AvPktCnt_Get()
7588 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL); in HAL_TSP_Debug_AvPktCnt_Get()
7601 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_V_PKT_CNT_CLR); in HAL_TSP_Debug_AvPktCnt_Clear()
7605 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_V3D_PKT_CNT_CLR); in HAL_TSP_Debug_AvPktCnt_Clear()
7609 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_A_PKT_CNT_CLR); in HAL_TSP_Debug_AvPktCnt_Clear()
7613 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_AD_PKT_CNT_CLR); in HAL_TSP_Debug_AvPktCnt_Clear()
7617 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_ADC_PKT_CNT_CLR); in HAL_TSP_Debug_AvPktCnt_Clear()
7621 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_ADD_PKT_CNT_CLR); in HAL_TSP_Debug_AvPktCnt_Clear()
7692 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V_LOAD); in HAL_TSP_Debug_DropPktCnt_Load()
7695 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V3D_LOAD); in HAL_TSP_Debug_DropPktCnt_Load()
7698 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_A_LOAD); in HAL_TSP_Debug_DropPktCnt_Load()
7701 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_AD_LOAD); in HAL_TSP_Debug_DropPktCnt_Load()
7704 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_ADC_LOAD); in HAL_TSP_Debug_DropPktCnt_Load()
7707 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_ADD_LOAD); in HAL_TSP_Debug_DropPktCnt_Load()
7747 REG16_SET(&_RegCtrl3->CFG3_37,HW4_CFG37_DIS_CNTR_INC_BY_PL); in HAL_TSP_Debug_DisPktCnt_Load()
7759 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V_LOAD); in HAL_TSP_Debug_DisPktCnt_Load()
7762 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_A_LOAD); in HAL_TSP_Debug_DisPktCnt_Load()
7765 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_AD_LOAD); in HAL_TSP_Debug_DisPktCnt_Load()
7768 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_ADC_LOAD); in HAL_TSP_Debug_DisPktCnt_Load()
7771 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_ADD_LOAD); in HAL_TSP_Debug_DisPktCnt_Load()
7808 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_DROP_PKT_MODE); in HAL_TSP_Debug_DropDisPktCnt_Get()
7840 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V_CLR); in HAL_TSP_Debug_DropPktCnt_Clear()
7844 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V3D_CLR); in HAL_TSP_Debug_DropPktCnt_Clear()
7848 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_A_CLR); in HAL_TSP_Debug_DropPktCnt_Clear()
7852 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_AD_CLR); in HAL_TSP_Debug_DropPktCnt_Clear()
7856 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_ADC_CLR); in HAL_TSP_Debug_DropPktCnt_Clear()
7860 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_ADD_CLR); in HAL_TSP_Debug_DropPktCnt_Clear()
7874 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
7878 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
7882 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
7886 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADC_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
7890 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADD_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
7932 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_0_LOAD); in HAL_TSP_Debug_ErrPktCnt_Load()
7935 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_1_LOAD); in HAL_TSP_Debug_ErrPktCnt_Load()
7938 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_2_LOAD); in HAL_TSP_Debug_ErrPktCnt_Load()
7941 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_3_LOAD); in HAL_TSP_Debug_ErrPktCnt_Load()
7982 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_0_CLR); in HAL_TSP_Debug_ErrPktCnt_Clear()
7986 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_1_CLR); in HAL_TSP_Debug_ErrPktCnt_Clear()
7990 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_2_CLR); in HAL_TSP_Debug_ErrPktCnt_Clear()
7994 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_3_CLR); in HAL_TSP_Debug_ErrPktCnt_Clear()
8037 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_0_LOAD); in HAL_TSP_Debug_InputPktCnt_Load()
8040 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_1_LOAD); in HAL_TSP_Debug_InputPktCnt_Load()
8043 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_2_LOAD); in HAL_TSP_Debug_InputPktCnt_Load()
8046 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_3_LOAD); in HAL_TSP_Debug_InputPktCnt_Load()
8086 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_0_CLR); in HAL_TSP_Debug_InputPktCnt_Clear()
8090 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_1_CLR); in HAL_TSP_Debug_InputPktCnt_Clear()
8094 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_2_CLR); in HAL_TSP_Debug_InputPktCnt_Clear()
8098 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_3_CLR); in HAL_TSP_Debug_InputPktCnt_Clear()
8129 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_FILTER_NULL_PKT); in HAL_TSP_FQ_FLT_NULL_PKT()