Lines Matching refs:REG16_SET
119 #define REG16_SET(reg, value) REG16_W(reg, _SET_(REG16_R(reg), value)) macro
273 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE); in HAL_TSP_HwPatch()
274 REG16_SET(&_RegOtherCtrl->CFG_OTHER_16, CFG_OHTER_16_REG_PREVENT_SRAM_COLLISION); in HAL_TSP_HwPatch()
278 …REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WST… in HAL_TSP_HwPatch()
294 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_RECORD_TS); in HAL_TSP_HwPatch()
300 … REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_0D, CFG_PVR_0D_REG_PVR_WRITE_POINTER_TO_NEXT_ADDRESS_EN); in HAL_TSP_HwPatch()
303 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_SKIP_PVR_RUSH_DATA); in HAL_TSP_HwPatch()
309 REG16_SET(&_RegPcrCtrl[u8Idx].CFG_PCR_00, CFG_PCR_00_REG_SKIP_PVR_RUSH_DATA); in HAL_TSP_HwPatch()
314 …REG16_SET(&_RegAudioCtrl[u8Idx].CFG_AV_00, (CFG_AV_00_REG_DUP_PKT_SKIP | CFG_AV_00_REG_PUSI_THREE_… in HAL_TSP_HwPatch()
319 …REG16_SET(&_RegVideoCtrl[u8Idx].CFG_AV_00, (CFG_AV_00_REG_DUP_PKT_SKIP | CFG_AV_00_REG_PUSI_THREE_… in HAL_TSP_HwPatch()
323 …REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ2PINGPONG_EN | TSP_RM_PKT_DEMUX_PIPE /*| TSP_PVR1_ALIGN_EN… in HAL_TSP_HwPatch()
328 REG16_SET(&_RegCtrl->reg160C, TSP_DOUBLE_BUF_DESC); in HAL_TSP_HwPatch()
329 REG16_SET(&_RegOtherCtrl->CFG_OTHER_16, CFG_OHTER_16_REG_FIX_PINPON_SYNCP_IN); in HAL_TSP_HwPatch()
331 REG16_SET(&_RegCtrl->reg160E, TSP_RM_DMA_GLITCH); in HAL_TSP_HwPatch()
333 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_HwPatch()
335 REG16_SET(&_RegCtrl->PVRConfig, TSP_MATCH_PID_LD); in HAL_TSP_HwPatch()
339 REG16_SET(&_RegPathCtrl[u8Idx].CFG_PATH_08, CFG_PATH_08_REG_BLK_AF_SCRMB_BIT_TSP); in HAL_TSP_HwPatch()
342 REG16_SET(&_RegPathCtrl[u8Idx].CFG_PATH_06, CFG_PATH_06_REG_ECO_TS_SYNC_OUT_DELAY); in HAL_TSP_HwPatch()
343 REG16_SET(&_RegPathCtrl[u8Idx].CFG_PATH_06, CFG_PATH_06_REG_ECO_TS_SYNC_OUT_REVERSE_BLOCK); in HAL_TSP_HwPatch()
346 REG16_SET(&_RegPathCtrl[u8Idx].CFG_PATH_06, CFG_PATH_06_REG_FIX_FILTER_NULL_PKT); in HAL_TSP_HwPatch()
350 REG16_SET(&_RegCtrl->reg15b8, TSP_SERIAL_EXT_SYNC_1T); in HAL_TSP_HwPatch()
351 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_SYNC_RISING_DETECT); in HAL_TSP_HwPatch()
352 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_VALID_FALLING_DETECT) in HAL_TSP_HwPatch()
355 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_DATA_CHK_2T); in HAL_TSP_HwPatch()
363 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_0A, CFG_FILE_0A_REG_FIX_192_TIMER_0_EN); in HAL_TSP_HwPatch()
366 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_0A, CFG_FILE_0A_REG_INIT_STAMP_RSTART_EN); in HAL_TSP_HwPatch()
370 REG16_SET(&_RegOtherCtrl->CFG_OTHER_14, CFG_OHTER_14_REG_CPU_LOAD_CODE_ONLY_ONE_TIME_BY_TEE); in HAL_TSP_HwPatch()
373 REG16_SET(&_RegOtherCtrl->CFG_OTHER_75, CFG_OTHER_75_REG_FIXED_MIU_REQ_FLUSH); in HAL_TSP_HwPatch()
376 REG16_SET(&_RegTopCtrl->CFG_TOP_24, CFG_TOP_24_REG_MIU_FIXED_LAST_WD_EN_DONE_Z_ABT_ALL); in HAL_TSP_HwPatch()
377 REG16_SET(&_RegTopCtrl->CFG_TOP_25, CFG_TOP_25_REG_CHECK_MI2RDY_ABT_ALL); in HAL_TSP_HwPatch()
378 …REG16_SET(&_RegOtherCtrl->CFG_OTHER_14, CFG_OHTER_14_REG_OR_WRITE_FIX_FOR_NEW_MIU_ARBITER_DISABLE); in HAL_TSP_HwPatch()
419 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
424 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
544 REG16_SET(&_RegOtherCtrl->CFG_OTHER_16, CFG_OHTER_16_REG_PREVENT_SRAM_COLLISION); in HAL_TSP_Power()
547 REG16_SET(&_RegOtherCtrl->CFG_OTHER_13, CFG_OHTER_13_REG_TSP2MI_REQ_MCM_DISABLE) in HAL_TSP_Power()
639 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_CPU()
677 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START); in HAL_TSP_LoadFW()
768 REG16_SET(&_RegPathCtrl[tsIf].CFG_PATH_00, CFG_PATH_00_REG_TS_IF_EN); in HAL_TSP_TSIF_LiveEn()
1138 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_00, CFG_FILE_00_REG_TSP_FILE_SEGMENT); in HAL_TSP_TSIF_FileEn()
1139 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_TS_DATA_PORT_SEL); in HAL_TSP_TSIF_FileEn()
1140 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_00, CFG_FILE_00_REG_TSP_FILE_IN); in HAL_TSP_TSIF_FileEn()
1162 REG16_SET(&_RegPathCtrl[tsIf].CFG_PATH_00, CFG_PATH_00_REG_TS_DATA_SWAP); in HAL_TSP_TSIF_BitSwap()
1180 REG16_SET(&_RegPathCtrl[tsIf].CFG_PATH_00, CFG_PATH_00_REG_EXT_SYNC_SEL); in HAL_TSP_TSIF_ExtSync()
1201 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_PS_MODE_BLOCK); in HAL_TSP_Filein_Bypass()
1219 REG16_SET(&_RegPathCtrl[tsIf].CFG_PATH_00, CFG_PATH_00_REG_P_SEL); in HAL_TSP_TSIF_Parl()
1242 REG16_SET(&_RegOtherCtrl->CFG_OTHER_13, (CFG_OTHER_13_REG_3WIRE_SERIAL_MODE_EN << tsIf)); in HAL_TSP_TSIF_3Wire()
1281 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_0E, u16value); in HAL_TSP_Filein_PktSize()
1340 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_06, CFG_FILE_06_REG_FILEIN_RSTART); in HAL_TSP_Filein_Start()
1354 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_TSIF_PAUSE); in HAL_TSP_File_Pause()
1391 …REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_06, (CFG_FILE_06_REG_FILEIN_RSTART | CFG_FILE_06_REG_FI… in HAL_TSP_Filein_Init_Trust_Start()
1404 … REG16_SET(&_RegOtherCtrl->CFG_OTHER_19, (CFG_OTHER_19_REG_FILEIN0_DMAR_PROTECT_EN << eFileEng)); in HAL_TSP_FILEIN_Address_Protect_En()
1451 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_TSP_FILEIN_ABORT); in HAL_TSP_Filein_Abort()
1472 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_00, CFG_FILE_00_REG_RST_CMDQ_FILEIN); in HAL_TSP_Filein_CmdQRst()
1536 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_TIMER_EN); in HAL_TSP_Filein_ByteDelay()
1602 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_PKT192_EN); in HAL_TSP_Filein_PacketMode()
1627 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_PKT192_BLK_DISABLE); in HAL_TSP_Filein_BlockTimeStamp()
1642 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_LPCR2_WLD); in HAL_TSP_Filein_SetTimeStamp()
1663 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_LPCR_FREG_27M_90K); in HAL_TSP_Filein_SetTimeStampClk()
1686 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_00, CFG_FILE_00_REG_LPCR2_LOAD); in HAL_TSP_Filein_GetTimeStamp()
1732 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_00, CFG_FILE_00_REG_WB_FSM_RESET); in HAL_TSP_Filein_WbFsmRst()
1842 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SEC_DMA_BURST_EN); in HAL_TSP_SecFlt_BurstLen()
2209 REG16_SET(&_RegPcrCtrl[pcrFltId].CFG_PCR_00, CFG_PCR_00_REG_PCR_READ); in HAL_TSP_PcrFlt_GetPcr()
2224 REG16_SET(&_RegPcrCtrl[pcrFltId].CFG_PCR_00, CFG_PCR_00_REG_PCR_RESET); in HAL_TSP_PcrFlt_Reset()
2232 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR0_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2236 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR1_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2240 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR2_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2244 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR3_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2248 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR4_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2252 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR5_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2256 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR6_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2260 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR7_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2519 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_STC64_Mode_En()
2564 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC64_Get()
2570 REG16_SET(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld); in HAL_TSP_STC64_Get()
2604 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC33_CmdQGet()
2656 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_REG_BD_AUD_EN); in HAL_TSP_FIFO_BD_AUD_En()
2660 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_REG_MAIN_CHANNEL); in HAL_TSP_FIFO_BD_AUD_En()
2751 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_06, CFG_AV_06_REG_PES_RSEL); in HAL_TSP_FIFO_ReadEn()
2764 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_06, CFG_AV_06_REG_PES_RSEL); in HAL_TSP_FIFO_ReadEn()
2806 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_06, CFG_AV_06_REG_FIFO_RD); in HAL_TSP_FIFO_Connect()
2819 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_06, CFG_AV_06_REG_FIFO_RD); in HAL_TSP_FIFO_Connect()
2861 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_TRACE_MARK_EN); in HAL_TSP_TRACE_MARK_En()
2874 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_TRACE_MARK_EN); in HAL_TSP_TRACE_MARK_En()
2899 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_PID_BYPASS); in HAL_TSP_Flt_Bypass()
2912 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_PID_BYPASS); in HAL_TSP_Flt_Bypass()
2935 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_PS_MODE); in HAL_TSP_FIFO_Bypass()
2948 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_PS_MODE); in HAL_TSP_FIFO_Bypass()
2991 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_01, CFG_AV_01_REG_RESET_FIFO_PARSER); in HAL_TSP_FIFO_Reset()
3004 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_01, CFG_AV_01_REG_RESET_FIFO_PARSER); in HAL_TSP_FIFO_Reset()
3027 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_MASK_SCR_EN); in HAL_TSP_FIFO_Skip_Scrmb()
3040 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_MASK_SCR_EN); in HAL_TSP_FIFO_Skip_Scrmb()
3061 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_BLOCK_DISABLE); in HAL_TSP_FIFO_BlockDis()
3074 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_BLOCK_DISABLE); in HAL_TSP_FIFO_BlockDis()
3268 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN); in HAL_TSP_VQ_Enable()
3286 REG16_SET(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_ctrl, REG_OTHER_VQ_TX_REG_VQ_RESET); in HAL_TSP_VQ_Reset()
3306 REG16_SET(&_RegOtherCtrl->CFG_OTHER_75, (CFG_OTHER_75_REG_VQ_TX_BLOCK_DISABLE << vqId)); in HAL_TSP_VQ_Block_Dis()
3326 …REG16_SET(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_ctrl, REG_OTHER_VQ_TX_REG_VQ_OVERFLOW_INT_E… in HAL_TSP_VQ_OverflowInt_En()
3342 …REG16_SET(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_ctrl, REG_OTHER_VQ_TX_REG_VQ_CLR_OVERFLOW_I… in HAL_TSP_VQ_OverflowInt_Clr()
3359 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_PINGPONG_EN); in HAL_PVR_Init()
3379 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_STR2MI_RST_WADR); in HAL_PVR_Exit()
3398 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_STR2MI_RST_WADR); in HAL_PVR_Start()
3402 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_STR2MI_EN); in HAL_PVR_Start()
3433 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_STR2MI_PAUSE); in HAL_PVR_Pause()
3458 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_RECORD_ALL); in HAL_PVR_RecPid()
3477 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
3496 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_0D, CFG_PVR_0D_REG_FLUSH_PVR_DATA); in HAL_PVR_FlushData()
3513 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_MASK_SCR_PVR_EN); in HAL_PVR_Skip_Scrmb()
3534 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_PVR_BLOCK_DISABLE); in HAL_PVR_Block_Dis()
3579 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_0D, CFG_PVR_0D_REG_PVR_TIMESTAMP_SRC_SEL); in HAL_PVR_TimeStamp_Sel()
3611 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_26, CFG_PVR_26_REG_BYPASS_TIMESTAMP_SEL); in HAL_PVR_PauseTime_En()
3646 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_DIS_NULL_PKT); in HAL_PVR_RecNull()
4087 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_PKT192_EN); in HAL_PVR_SetStrPacketMode()
4110 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
4127 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
4316 REG16_SET(&_RegCtrl->DBG_SEL, ((u16Sel << TSP_DBG_SEL_SHIFT) & TSP_DBG_SEL_MASK)); in HAL_TSP_GetDBGStatus()
4334 REG16_SET(&_RegCtrl->HwInt_Stat, (TSP_HWINT_EN_MASK & u32Mask)); in HAL_TSP_INT_Enable()
4345 REG16_SET(&_RegCtrl->HwInt2_Stat, (TSP_HWINT2_EN_MASK & (u32Mask >> 8))); in HAL_TSP_INT_Enable()
4358 REG16_SET(&_RegCtrl->HwInt3_Stat, (TSP_HWINT3_EN_MASK & (u32Mask >> 16))); in HAL_TSP_INT_Enable()
4379 REG16_SET(&_RegCtrl->HwInt_Stat, ((u32Mask << TSP_HWINT_STATUS_SHIFT) & TSP_HWINT_STATUS_MASK)); in HAL_TSP_INT_ClrHW()
4382 …REG16_SET(&_RegCtrl->HwInt2_Stat, (((u32Mask >> 8) << TSP_HWINT2_STATUS_SHIFT) & TSP_HWINT2_STATUS… in HAL_TSP_INT_ClrHW()
4385 …REG16_SET(&_RegCtrl->HwInt3_Stat, (((u32Mask >> 16) << TSP_HWINT3_STATUS_SHIFT) & TSP_HWINT3_STATU… in HAL_TSP_INT_ClrHW()
4430 REG16_SET(&_RegFile0Ctrl[u8FileEng].CFG_FILE_0F, CFG_FILE_0F_REG_SPD_TSIF_BYPASS); in HAL_TSP_SPD_Bypass_En()
4435 REG16_SET(&_RegFile1Ctrl[u8FileEng].CFG_FILE_0F, CFG_FILE_0F_REG_SPD_TSIF_BYPASS); in HAL_TSP_SPD_Bypass_En()
4462 …REG16_SET(&_RegSpdCtrl[tsIf].CFG_SPD_05, CFG_SPD_05_REG_CTR_MODE_SPD_FILEIN); //set CTR mode ena… in HAL_TSP_FileIn_SPDConfig()
4468 … REG16_SET(&_RegSpdCtrl[tsIf].CFG_SPD_05, CFG_SPD_05_REG_LOAD_INIT_COUNTER_SPD); //load counter IV in HAL_TSP_FileIn_SPDConfig()
4488 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_0F, CFG_FILE_0F_REG_LOAD_SPD_KEY); in HAL_TSP_FileIn_SPDConfig()
4490 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_0F, CFG_FILE_0F_REG_TSIF_SPD_RST); in HAL_TSP_FileIn_SPDConfig()
4631 REG16_SET(&_RegAudioCtrl[u8Idx].CFG_AV_00, CFG_AV_00_REG_DUP_PKT_SKIP); in HAL_TSP_PktDmx_RmDupAVPkt()
4636 REG16_SET(&_RegVideoCtrl[u8Idx].CFG_AV_00, CFG_AV_00_REG_DUP_PKT_SKIP); in HAL_TSP_PktDmx_RmDupAVPkt()
4661 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_PES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
4674 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_PES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
4699 REG16_SET(&_RegPathCtrl[tsIf].CFG_PATH_08, CFG_PATH_08_REG_TEI_SKIP_PKT); in HAL_TSP_TEI_SKIP()
4713 REG16_SET(&_RegCtrl->reg160C, TSP_ORZ_DMAW_PROT_EN); in HAL_TSP_OR_Address_Protect_En()
4740 REG16_SET(&_RegCtrl->reg15b4, TSP_SEC_CB_PVR2_DAMW_PROTECT_EN); in HAL_TSP_SEC_Address_Protect_En()
4790 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_0D, CFG_PVR_0D_REG_PVR_DMAW_PROTECT_EN); in HAL_TSP_PVR_Address_Protect_En()
4835 … REG16_SET(&_RegOtherCtrl->CFG_OTHER_18, (CFG_OTHER_18_REG_MMFI0_DMAR_PROTECT_EN << u32MMFIEng)); in HAL_TSP_MMFI_Address_Protect_En()
4931 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_10, CFG_PVR_10_REG_REC_CA_UPPER_PATH); in HAL_TSP_CAPVR_SPSEnable()
4934 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_1B, CFG_PVR_1B_REG_PKT_192_SPS_EN); in HAL_TSP_CAPVR_SPSEnable()
4973 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_1B, CFG_PVR_1B_REG_PKT_192_SPS_EN); in HAL_TSP_PVR_SPSConfig()
4983 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_1B, CFG_PVR_1B_REG_LOAD_SPS_KEY); in HAL_TSP_PVR_SPSConfig()
4987 …REG16_SET(&RegSpsCtrl[u8PvrEng].CFG_SPS_05, CFG_SPS_05_REG_CTR_MODE_SPS_PVR); //set CTR mo… in HAL_TSP_PVR_SPSConfig()
4993 …REG16_SET(&RegSpsCtrl[u8PvrEng].CFG_SPS_05, CFG_SPS_05_REG_LOAD_INIT_COUNTER_SPS); //load count… in HAL_TSP_PVR_SPSConfig()
5126 REG16_SET(SrcIdReg, (CFG_TSP_MULTI_SRC_ID_MULTI_SYNC_BYTE_EN << u16Shift)); // enable bit in HAL_TSP_PktConverter_SetSrcId()
5221 …REG16_SET(PktConverterReg, CFG_PATH_05_PKT_CONVERTER_FORCE_SYNCBYTE); // Set 1 to force sync byte … in HAL_TSP_PktConverter_ForceSync()
5255 REG16_SET(PktConverterReg, CFG_PATH_05_SRC_ID_FLT_EN); in HAL_TSP_PktConverter_SrcIdFlt()
5321 REG16_SET(&_RegPathCtrl[u32TsIf].CFG_PATH_02, CFG_PATH_02_REG_LOCKED_PKT_CNT_LOAD); in HAL_TSP_Debug_LockPktCnt_Load()
5343 REG16_SET(&_RegPathCtrl[u32TsIf].CFG_PATH_02, CFG_PATH_02_REG_UNLOCKED_PKT_CNT_MODE); in HAL_TSP_Debug_LockPktCnt_Get()
5357 REG16_SET(&_RegPathCtrl[u32TsIf].CFG_PATH_02, CFG_PATH_02_REG_LOCKED_PKT_CNT_CLR); in HAL_TSP_Debug_LockPktCnt_Clear()
5379 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_PKT_CNT_LOAD); in HAL_TSP_Debug_AvPktCnt_Load()
5392 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_PKT_CNT_LOAD); in HAL_TSP_Debug_AvPktCnt_Load()
5432 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_PKT_CNT_CLR); in HAL_TSP_Debug_AvPktCnt_Clear()
5439 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_PKT_CNT_CLR); in HAL_TSP_Debug_AvPktCnt_Clear()
5461 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_DROP_PKT_CNT_LOAD); in HAL_TSP_Debug_DropPktCnt_Load()
5474 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_DROP_PKT_CNT_LOAD); in HAL_TSP_Debug_DropPktCnt_Load()
5495 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_INC_BY_PL); in HAL_TSP_Debug_DisPktCnt_Load()
5504 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_LOAD); in HAL_TSP_Debug_DisPktCnt_Load()
5517 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_INC_BY_PL); in HAL_TSP_Debug_DisPktCnt_Load()
5526 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_LOAD); in HAL_TSP_Debug_DisPktCnt_Load()
5580 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_DROP_PKT_CNT_CLR); in HAL_TSP_Debug_DropPktCnt_Clear()
5587 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_DROP_PKT_CNT_CLR); in HAL_TSP_Debug_DropPktCnt_Clear()
5602 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
5609 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
5635 REG16_SET(&_RegPathCtrl[u32TsIf].CFG_PATH_0C, CFG_PATH_0C_REG_ERR_PKT_CNTR_LOAD); in HAL_TSP_Debug_ErrPktCnt_Load()
5662 REG16_SET(&_RegPathCtrl[u32TsIf].CFG_PATH_0C, CFG_PATH_0C_REG_ERR_PKT_CNTR_CLR); in HAL_TSP_Debug_ErrPktCnt_Clear()
5711 REG16_SET(&_RegPathCtrl[u32FQEng].CFG_PATH_06, CFG_PATH_06_REG_FILTER_NULL_PKT); in HAL_TSP_FQ_FLT_NULL_PKT()
5759 REG16_SET(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_PATH0 << u32Eng); in HAL_TSP_CLK_GATING()
5763 REG16_SET(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_TSP_ENG); in HAL_TSP_CLK_GATING()
5766 REG16_SET(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_FIQ); in HAL_TSP_CLK_GATING()
5778 REG16_SET(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_PVR1 << u32Eng); in HAL_TSP_CLK_GATING()
5792 REG16_SET(&_RegCtrl6->CFG6_7F,CFG6_7F_REG_MIU_CLK_GATING_PATH0 << u32Eng); in HAL_TSP_CLK_GATING()
5796 REG16_SET(&_RegCtrl6->CFG6_7F,CFG6_7F_REG_MIU_CLK_GATING_TSP_ENG); in HAL_TSP_CLK_GATING()
5810 REG16_SET(&_RegCtrl6->CFG6_6D,CFG6_6D_REG_CLK_GATING_FIQ0 << u32Eng); in HAL_TSP_CLK_GATING()
5824 REG16_SET(&_RegCtrl6->CFG6_6D,CFG6_6D_REG_MIU_CLK_GATING_FIQ0 << u32Eng); in HAL_TSP_CLK_GATING()
5933 REG16_SET(&_RegCtrl6->CFG6_7A,CFG6_7A_REG_CLK_RESET_PKT_CONVERTER0 << u32Idx); in HAL_TSP_Module_Reset()
5938 REG16_SET(&_RegCtrl6->CFG6_7A,CFG6_7A_REG_CLK_RESET_FIQ0 << u32Idx); in HAL_TSP_Module_Reset()
5943 REG16_SET(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_VQ_TX0 << u32Idx); in HAL_TSP_Module_Reset()
5946 REG16_SET(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_VQ_RX); in HAL_TSP_Module_Reset()
5949 REG16_SET(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_VQ_TOP); in HAL_TSP_Module_Reset()
5954 REG16_SET(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_PKT_DEMUX0 << u32Idx); in HAL_TSP_Module_Reset()
5959 REG16_SET(&_RegCtrl6->CFG6_7C,CFG6_7C_REG_RESET_PVR1 << u32Idx); in HAL_TSP_Module_Reset()
5964 REG16_SET(&_RegCtrl6->CFG6_7C,CFG6_7C_REG_RESET_TIMESTAMP_SEL_PVR1 << u32Idx); in HAL_TSP_Module_Reset()
5969 REG16_SET(&_RegCtrl6->CFG6_7C,CFG6_7C_REG_RESET_SP_D0 << u32Idx); in HAL_TSP_Module_Reset()
5974 REG16_SET(&_RegCtrl6->CFG6_7D,CFG6_7D_REG_RESET_FILTER_NULL_PKT0 << u32Idx); in HAL_TSP_Module_Reset()
5979 REG16_SET(&_RegCtrl6->CFG6_7D,CFG6_7D_REG_RESET_DIRECTV_130_188_0 << u32Idx); in HAL_TSP_Module_Reset()
5984 REG16_SET(&_RegCtrl6->CFG6_7E,CFG6_7E_REG_RESET_SRC_ID_PARSER0 << u32Idx); in HAL_TSP_Module_Reset()
5989 REG16_SET(&_RegCtrl6->CFG6_7E,CFG6_7E_REG_RESET_PCRFLT_0 << u32Idx); in HAL_TSP_Module_Reset()
5994 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_PATH0 << u32Idx); in HAL_TSP_Module_Reset()
5997 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_OTV); in HAL_TSP_Module_Reset()
6000 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_DEBUG_TABLE); in HAL_TSP_Module_Reset()
6003 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_DMA_ENG); in HAL_TSP_Module_Reset()
6006 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_SEC_CMP); in HAL_TSP_Module_Reset()
6009 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_SECFLT_REG); in HAL_TSP_Module_Reset()
6012 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_SEC); in HAL_TSP_Module_Reset()
6015 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_PID_TABLE); in HAL_TSP_Module_Reset()