Lines Matching refs:REG16_SET
111 #define REG16_SET(reg, value) REG16_W(reg, _SET_(REG16_R(reg), value)) macro
250 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE); in HAL_TSP_HwPatch()
251 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_HwPatch()
255 …REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WST… in HAL_TSP_HwPatch()
264 REG16_SET(&_RegCtrl->reg15b4, TSP_PVR_PID_BYPASS|TSP_PVR_PID_BYPASS2); in HAL_TSP_HwPatch()
265 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PID_BYPASS3_REC); in HAL_TSP_HwPatch()
266 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PID_BYPASS4_REC); in HAL_TSP_HwPatch()
268 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT); in HAL_TSP_HwPatch()
270 …REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ2PINGPONG_EN | TSP_RM_PKT_DEMUX_PIPE /*| TSP_PVR1_ALIGN_EN… in HAL_TSP_HwPatch()
273 …REG16_SET(&_RegCtrl->reg160C, TSP_DOUBLE_BUF_DESC/*| TSP_VQTX0_BLOCK_DIS|TSP_VQTX2_BLOCK_DIS|TSP_V… in HAL_TSP_HwPatch()
274 REG16_SET(&_RegCtrl->reg160E, TSP_RM_DMA_GLITCH); in HAL_TSP_HwPatch()
276 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PUSI_3BYTE_MODE); //Enable audio 3 byte mode in HAL_TSP_HwPatch()
278 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_HwPatch()
279 REG16_SET(&_RegCtrl->PVRConfig, TSP_MATCH_PID_LD); in HAL_TSP_HwPatch()
280 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BLK_AD_SCMBTIS_TSP); in HAL_TSP_HwPatch()
287 REG16_SET(&_RegCtrl3->CFG3_16, CFG3_16_FIXED_DMA_RSTART_OTP_ONEWAY_LOAD_FW); in HAL_TSP_HwPatch()
290 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_DATA_CHK_2T); in HAL_TSP_HwPatch()
293 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_FIX_192_TIMER_0_EN); in HAL_TSP_HwPatch()
299 REG16_SET(&_RegCtrl6->CFG6_2A, FIXED_DMA_WADDR_NEXT_OVF | FIXED_VQ_MIU_REQ_FLUSH); in HAL_TSP_HwPatch()
302 REG16_SET(&_RegCtrl6->CFG6_2A, TSP_DROP_ERR_START_CODE | TSP_DROP_TEI_ERR_START_CODE); in HAL_TSP_HwPatch()
304 REG16_SET(&_RegCtrl6->CFG6_2A,TSP_FIQ_DMA_FLUSH_EN | TSP_FIND_LOSS_SYNC_PID_RVU); in HAL_TSP_HwPatch()
307 …REG16_SET(&_RegCtrl6->CFG6_2B, TSP_ECO_FIQ_INPUT | TSP_ECO_TS_SYNC_OUT_DELAY | TSP_ECO_TS_SYNC_OUT… in HAL_TSP_HwPatch()
310 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_SYNC_RISING_DETECT | TSP_VALID_FALLING_DETECT); in HAL_TSP_HwPatch()
350 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Reset()
351 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
352 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Reset()
353 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Reset()
354 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
359 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
377 REG16_SET(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET); in HAL_TSP_Path_Reset()
378 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0); in HAL_TSP_Path_Reset()
379 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0); in HAL_TSP_Path_Reset()
390 REG16_SET(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1); in HAL_TSP_Path_Reset()
391 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1); in HAL_TSP_Path_Reset()
392 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1); in HAL_TSP_Path_Reset()
403 REG16_SET(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2); in HAL_TSP_Path_Reset()
404 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2); in HAL_TSP_Path_Reset()
405 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2); in HAL_TSP_Path_Reset()
441 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE); //TSP in HAL_TSP_Power()
442 …REG16_SET(&_RegCtrl3->CFG3_16, CFG3_16_MMFI1_REQ_MCM_DISABLE); // disable MMFI1 MCM, and never ena… in HAL_TSP_Power()
477 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_Power()
514 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_CPU()
530 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_ResetCPU()
558 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START); in HAL_TSP_LoadFW()
622 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0); in HAL_TSP_PktBuf_Reset()
625 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1); in HAL_TSP_PktBuf_Reset()
628 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2); in HAL_TSP_PktBuf_Reset()
660 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0); in HAL_TSP_RecvBuf_Reset()
663 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1); in HAL_TSP_RecvBuf_Reset()
666 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2); in HAL_TSP_RecvBuf_Reset()
722 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE); in HAL_TSP_TSIF_LiveEn()
725 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE); in HAL_TSP_TSIF_LiveEn()
945 …REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); // for wishbone DMA (load firm… in HAL_TSP_TSIF_FileEn()
946 … REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL); //Tsif0 output is live TS in HAL_TSP_TSIF_FileEn()
947 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN); //filein enable in HAL_TSP_TSIF_FileEn()
950 …REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1); // for wishbone DMA (load firm… in HAL_TSP_TSIF_FileEn()
951 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1); in HAL_TSP_TSIF_FileEn()
952 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1); in HAL_TSP_TSIF_FileEn()
953 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN); //filein enable in HAL_TSP_TSIF_FileEn()
956 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2); in HAL_TSP_TSIF_FileEn()
957 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2); in HAL_TSP_TSIF_FileEn()
958 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2); in HAL_TSP_TSIF_FileEn()
959 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2); in HAL_TSP_TSIF_FileEn()
1001 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP); in HAL_TSP_TSIF_BitSwap()
1004 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP); in HAL_TSP_TSIF_BitSwap()
1041 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1044 REG16_SET(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1082 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP); in HAL_TSP_Filein_Bypass()
1085 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP1); in HAL_TSP_Filein_Bypass()
1088 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP2); in HAL_TSP_Filein_Bypass()
1123 REG16_SET(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL); in HAL_TSP_TSIF_Parl()
1126 REG16_SET(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL); in HAL_TSP_TSIF_Parl()
1208 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS0); in HAL_TSP_TSIF_3Wire()
1211 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS1); in HAL_TSP_TSIF_3Wire()
1214 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS2); in HAL_TSP_TSIF_3Wire()
1244 …REG16_SET(&_RegCtrl3->CFG3_0C, ((1 << pktDmxId) << CFG3_0C_PKTDMX_CC_DROP_SHIFT) & CFG3_0C_PKTDMX_… in HAL_TSP_PktDmx_CCDrop()
1280 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V_EN); in HAL_TSP_TRACE_MARK_En()
1283 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V3D_EN); in HAL_TSP_TRACE_MARK_En()
1286 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_A_EN); in HAL_TSP_TRACE_MARK_En()
1289 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_AB_EN); in HAL_TSP_TRACE_MARK_En()
1299 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V_EN); in HAL_TSP_TRACE_MARK_En()
1302 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V3D_EN); in HAL_TSP_TRACE_MARK_En()
1305 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_A_EN); in HAL_TSP_TRACE_MARK_En()
1308 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_AB_EN); in HAL_TSP_TRACE_MARK_En()
1318 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V_EN); in HAL_TSP_TRACE_MARK_En()
1321 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V3D_EN); in HAL_TSP_TRACE_MARK_En()
1324 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_A_EN); in HAL_TSP_TRACE_MARK_En()
1327 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_AB_EN); in HAL_TSP_TRACE_MARK_En()
1412 REG16_SET(&_RegCtrl->reg15b4, TSP_BD_AUD_EN); in HAL_TSP_BD_AUD_En()
1415 REG16_SET(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN); in HAL_TSP_BD_AUD_En()
1481 REG16_SET(&_RegCtrl3->CFG3_36, u16value); in HAL_TSP_Filein_PktSize()
1485 REG16_SET(&_RegCtrl3->CFG3_36, u16value); in HAL_TSP_Filein_PktSize()
1489 REG16_SET(&_RegCtrl4->CFG4_54, u16value); in HAL_TSP_Filein_PktSize()
1500 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_ALT_TS_SIZE); in HAL_TSP_Filein_PktSize()
1555 REG16_SET(&_RegCtrl->TsDma_Ctrl, TSP_TSDMA_CTRL_START); in HAL_TSP_Filein_Start()
1558 REG16_SET(&_RegCtrl2->CFG_34, CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START); in HAL_TSP_Filein_Start()
1561 REG16_SET(&_RegCtrl2->CFG_39, CFG_39_FILEIN_CTRL_TSIF2_START); in HAL_TSP_Filein_Start()
1573 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE); in HAL_TSP_File_Pause()
1576 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF1_FILE_PAUSE); in HAL_TSP_File_Pause()
1579 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF2_FILE_PAUSE); in HAL_TSP_File_Pause()
1609 REG16_SET(&_RegCtrl->TsDma_Ctrl, (TSP_TSDMA_INIT_TRUST | TSP_TSDMA_CTRL_START)); in HAL_TSP_Filein_Init_Trust_Start()
1612 …REG16_SET(&_RegCtrl2->CFG_34, (CFG_34_REG_TSP_FILEIN_INIT_TRUST_TSIF1 | CFG_34_REG_TSP_FILEIN_CTRL… in HAL_TSP_Filein_Init_Trust_Start()
1615 … REG16_SET(&_RegCtrl2->CFG_39, (CFG_39_FILEIN_INIT_TRUST_TSIF2 | CFG_39_FILEIN_CTRL_TSIF2_START)); in HAL_TSP_Filein_Init_Trust_Start()
1629 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0); in HAL_TSP_Filein_Abort()
1632 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1); in HAL_TSP_Filein_Abort()
1635 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2); in HAL_TSP_Filein_Abort()
1667 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Filein_CmdQRst()
1670 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Filein_CmdQRst()
1673 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Filein_CmdQRst()
1751 REG16_SET(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE); in HAL_TSP_Filein_ByteDelay()
1755 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1); in HAL_TSP_Filein_ByteDelay()
1759 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2); in HAL_TSP_Filein_ByteDelay()
1875 REG16_SET(&_RegCtrl->reg160C, TSP_FILEIN192_EN); in HAL_TSP_Filein_PacketMode()
1878 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1); in HAL_TSP_Filein_PacketMode()
1881 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2); in HAL_TSP_Filein_PacketMode()
1931 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN); in HAL_TSP_Filein_BlockTimeStamp()
1934 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1); in HAL_TSP_Filein_BlockTimeStamp()
1937 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2); in HAL_TSP_Filein_BlockTimeStamp()
1951 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_0); in _HAL_TSP_FILEIN_ResetPktTimeStamp()
1956 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_1); in _HAL_TSP_FILEIN_ResetPktTimeStamp()
1961 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_2); in _HAL_TSP_FILEIN_ResetPktTimeStamp()
1975 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_WLD); in HAL_TSP_Filein_SetTimeStamp()
1980 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1); in HAL_TSP_Filein_SetTimeStamp()
1985 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2); in HAL_TSP_Filein_SetTimeStamp()
2003 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF0_C27M); in HAL_TSP_Filein_SetTimeStampClk()
2013 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF1_C27M); in HAL_TSP_Filein_SetTimeStampClk()
2023 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF2_C27M); in HAL_TSP_Filein_SetTimeStampClk()
2043 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_RLD); in HAL_TSP_Filein_GetTimeStamp()
2048 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1); in HAL_TSP_Filein_GetTimeStamp()
2053 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2); in HAL_TSP_Filein_GetTimeStamp()
2104 REG16_SET(&_RegCtrl3->CFG3_53, CFG3_53_WB_FSM_REST); in HAL_TSP_Filein_WbFsmRst()
2107 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1); in HAL_TSP_Filein_WbFsmRst()
2110 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2); in HAL_TSP_Filein_WbFsmRst()
2258 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SEC_DMA_BURST_EN); in HAL_TSP_SecFlt_BurstLen()
2528 REG16_SET(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN); in HAL_TSP_PcrFlt_Enable()
2538 REG16_SET(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN); in HAL_TSP_PcrFlt_Enable()
2654 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ); in HAL_TSP_PcrFlt_GetPcr()
2660 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ); in HAL_TSP_PcrFlt_GetPcr()
2676 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET); in HAL_TSP_PcrFlt_Reset()
2680 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET); in HAL_TSP_PcrFlt_Reset()
2818 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_STC64_Mode_En()
2849 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC64_Get()
2855 REG16_SET(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld); in HAL_TSP_STC64_Get()
2873 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC33_CmdQGet()
2935 REG16_SET(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN); in HAL_TSP_FIFO_Connect()
2986 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS); in HAL_TSP_Flt_Bypass()
2989 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS); in HAL_TSP_Flt_Bypass()
2992 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_B_BYPASS); in HAL_TSP_Flt_Bypass()
2995 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_VPID_3D_BYPASS); in HAL_TSP_Flt_Bypass()
3041 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN); in HAL_TSP_FIFO_Bypass()
3044 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
3047 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN); in HAL_TSP_FIFO_Bypass()
3050 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN); in HAL_TSP_FIFO_Bypass()
3108 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO); in HAL_TSP_FIFO_Reset()
3111 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D); in HAL_TSP_FIFO_Reset()
3115 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO); in HAL_TSP_FIFO_Reset()
3118 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO2); in HAL_TSP_FIFO_Reset()
3156 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V_EN); in HAL_TSP_FIFO_Skip_Scrmb()
3159 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V3D_EN); in HAL_TSP_FIFO_Skip_Scrmb()
3162 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_A_EN); in HAL_TSP_FIFO_Skip_Scrmb()
3165 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AB_EN); in HAL_TSP_FIFO_Skip_Scrmb()
3431 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
3434 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
3437 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
3468 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN); in HAL_TSP_VQ_Enable()
3482 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET); in HAL_TSP_VQ_Reset()
3485 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET); in HAL_TSP_VQ_Reset()
3488 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET); in HAL_TSP_VQ_Reset()
3520 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
3523 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
3526 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
3558 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT); in HAL_TSP_VQ_OverflowInt_Clr()
3561 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
3564 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
3595 REG16_SET(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG); in HAL_PVR_Init()
3619 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
3647 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
3651 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE); in HAL_PVR_Start()
3688 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
3720 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS); in HAL_PVR_RecPid()
3724 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2); in HAL_PVR_RecPid()
3737 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN); in HAL_PVR_RecPid()
3741 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN); in HAL_PVR_RecPid()
3753 REG16_SET(&(_RegCtrl->PVRConfig), TSP_REC_NULL); in HAL_PVR_RecNull()
4116 REG16_SET(&_RegCtrl->reg160C, TSP_RECORD192_EN); in HAL_PVR_SetStrPacketMode()
4151 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
4172 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
4195 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0); in HAL_PVR_SetPVRTimeStamp_Stream()
4202 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1); in HAL_PVR_SetPVRTimeStamp_Stream()
4220 REG16_SET(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN); in HAL_PVR_Alignment_Enable()
4250 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR_DATA); in HAL_PVR_FlushData()
4254 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR1_DATA); in HAL_PVR_FlushData()
4269 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN); in HAL_PVR_Skip_Scrmb()
4272 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN); in HAL_PVR_Skip_Scrmb()
4352 REG16_SET((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng)); in HAL_PVR_TimeStamp_Sel()
4381 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1); in HAL_PVR_PauseTime_En()
4384 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL2); in HAL_PVR_PauseTime_En()
4411 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2)); in HAL_PVR_TimeStamp_Stream_En()
4618 REG16_SET(&_RegCtrl->PKT_CNT, ((u16Sel << TSP_DBG_SEL_SHIFT) & TSP_DBG_SEL_MASK)); in HAL_TSP_GetDBGStatus()
4636 REG16_SET(&_RegCtrl->HwInt_Stat, TSP_INT_EN_MASK & u32Mask); in HAL_TSP_INT_Enable()
4648 …REG16_SET(&_RegCtrl->SwInt_Stat1_L, (TSP_HWINT2_EN_MASK & (u32Mask >> 8)) | TSP_HWINT2_STATUS_MASK… in HAL_TSP_INT_Enable()
4727 …REG16_SET(&_RegCtrl3->CFG3_52, CFG3_52_SPD_TSIF0_BYPASS | CFG3_52_SPD_TSIF1_BYPASS | CFG3_52_SPD_T… in HAL_TSP_SPD_Bypass_En()
4742 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_CTR_MODE_SPD_FILEIN); //set CTR mode enable in HAL_TSP_FileIn_SPDConfig()
4748 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_LOAD_INIT_CNT_SPD); //load counter IV in HAL_TSP_FileIn_SPDConfig()
4762 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY0); in HAL_TSP_FileIn_SPDConfig()
4764 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF0_SPD_RESET); //TSIF SPD reset in HAL_TSP_FileIn_SPDConfig()
4786 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY1); in HAL_TSP_FileIn_SPDConfig()
4788 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF1_SPD_RESET); //TSIF SPD reset in HAL_TSP_FileIn_SPDConfig()
4810 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY2); in HAL_TSP_FileIn_SPDConfig()
4812 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF2_SPD_RESET); //TSIF SPD reset in HAL_TSP_FileIn_SPDConfig()
5047 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT); in HAL_TSP_PktDmx_RmDupAVPkt()
5062 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
5065 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
5094 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0); in HAL_TSP_TEI_SKIP()
5097 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1); in HAL_TSP_TEI_SKIP()
5131 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR); in HAL_TSP_DisPKTCnt_Clear()
5135 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_DisPKTCnt_Clear()
5139 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR); in HAL_TSP_DisPKTCnt_Clear()
5143 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR); in HAL_TSP_DisPKTCnt_Clear()
5171 REG16_SET(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN); in HAL_TSP_OR_Address_Protect_En()
5192 REG16_SET(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN); in HAL_TSP_SEC_Address_Protect_En()
5228 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR1_DMAW_PROTECT_EN); in HAL_TSP_PVR_Address_Protect_En()
5231 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR2_DMAW_PROTECT_EN); in HAL_TSP_PVR_Address_Protect_En()
5281 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN0_DMAR_PROTECT_EN); in HAL_TSP_FILEIN_Address_Protect_En()
5284 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN1_DMAR_PROTECT_EN); in HAL_TSP_FILEIN_Address_Protect_En()
5287 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN2_DMAR_PROTECT_EN); in HAL_TSP_FILEIN_Address_Protect_En()
5344 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_MMFI0_DMAR_PROTECT_EN); in HAL_TSP_MMFI_Address_Protect_En()
5347 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_MMFI1_DMAR_PROTECT_EN); in HAL_TSP_MMFI_Address_Protect_En()
5476 case 0: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN1); in HAL_TSP_PVR_SPSConfig()
5486 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY1); in HAL_TSP_PVR_SPSConfig()
5488 case 1: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN2); in HAL_TSP_PVR_SPSConfig()
5508 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY2); in HAL_TSP_PVR_SPSConfig()
5517 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1); //set CTR mode in HAL_TSP_PVR_SPSConfig()
5523 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1); //load counter IV in HAL_TSP_PVR_SPSConfig()
5853 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_0_LOAD); in HAL_TSP_Debug_LockPktCnt_Load()
5856 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_1_LOAD); in HAL_TSP_Debug_LockPktCnt_Load()
5859 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_2_LOAD); in HAL_TSP_Debug_LockPktCnt_Load()
5895 REG16_SET(&_RegCtrl3->CFG3_37,HW4_CFG37_NON_188_CNT_MODE); in HAL_TSP_Debug_LockPktCnt_Get()
5906 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_0_CLR); in HAL_TSP_Debug_LockPktCnt_Clear()
5910 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_1_CLR); in HAL_TSP_Debug_LockPktCnt_Clear()
5914 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_2_CLR); in HAL_TSP_Debug_LockPktCnt_Clear()
6007 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_V_PKT_CNT_LOAD); in HAL_TSP_Debug_AvPktCnt_Load()
6010 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_V3D_PKT_CNT_LOAD); in HAL_TSP_Debug_AvPktCnt_Load()
6013 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_A_PKT_CNT_LOAD); in HAL_TSP_Debug_AvPktCnt_Load()
6016 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_AD_PKT_CNT_LOAD); in HAL_TSP_Debug_AvPktCnt_Load()
6057 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL); in HAL_TSP_Debug_AvPktCnt_Get()
6060 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL); in HAL_TSP_Debug_AvPktCnt_Get()
6073 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_V_PKT_CNT_CLR); in HAL_TSP_Debug_AvPktCnt_Clear()
6077 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_V3D_PKT_CNT_CLR); in HAL_TSP_Debug_AvPktCnt_Clear()
6081 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_A_PKT_CNT_CLR); in HAL_TSP_Debug_AvPktCnt_Clear()
6085 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_AD_PKT_CNT_CLR); in HAL_TSP_Debug_AvPktCnt_Clear()
6147 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V_LOAD); in HAL_TSP_Debug_DropPktCnt_Load()
6150 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V3D_LOAD); in HAL_TSP_Debug_DropPktCnt_Load()
6153 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_A_LOAD); in HAL_TSP_Debug_DropPktCnt_Load()
6156 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_AD_LOAD); in HAL_TSP_Debug_DropPktCnt_Load()
6190 REG16_SET(&_RegCtrl3->CFG3_37,HW4_CFG37_DIS_CNTR_INC_BY_PL); in HAL_TSP_Debug_DisPktCnt_Load()
6202 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V_LOAD); in HAL_TSP_Debug_DisPktCnt_Load()
6205 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V3D_LOAD); in HAL_TSP_Debug_DisPktCnt_Load()
6208 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_A_LOAD); in HAL_TSP_Debug_DisPktCnt_Load()
6211 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_AD_LOAD); in HAL_TSP_Debug_DisPktCnt_Load()
6245 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_DROP_PKT_MODE); in HAL_TSP_Debug_DropDisPktCnt_Get()
6277 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V_CLR); in HAL_TSP_Debug_DropPktCnt_Clear()
6281 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V3D_CLR); in HAL_TSP_Debug_DropPktCnt_Clear()
6285 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_A_CLR); in HAL_TSP_Debug_DropPktCnt_Clear()
6289 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_AD_CLR); in HAL_TSP_Debug_DropPktCnt_Clear()
6303 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
6307 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
6311 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
6315 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
6354 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_0_LOAD); in HAL_TSP_Debug_ErrPktCnt_Load()
6357 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_1_LOAD); in HAL_TSP_Debug_ErrPktCnt_Load()
6360 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_2_LOAD); in HAL_TSP_Debug_ErrPktCnt_Load()
6398 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_0_CLR); in HAL_TSP_Debug_ErrPktCnt_Clear()
6402 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_1_CLR); in HAL_TSP_Debug_ErrPktCnt_Clear()
6406 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_2_CLR); in HAL_TSP_Debug_ErrPktCnt_Clear()
6445 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_0_LOAD); in HAL_TSP_Debug_InputPktCnt_Load()
6448 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_1_LOAD); in HAL_TSP_Debug_InputPktCnt_Load()
6451 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_2_LOAD); in HAL_TSP_Debug_InputPktCnt_Load()
6488 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_0_CLR); in HAL_TSP_Debug_InputPktCnt_Clear()
6492 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_1_CLR); in HAL_TSP_Debug_InputPktCnt_Clear()
6496 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_2_CLR); in HAL_TSP_Debug_InputPktCnt_Clear()