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Searched refs:OPENRISC_IP_3_ADDR (Results 1 – 22 of 22) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/
H A DregTSP.h1195 #define OPENRISC_IP_3_ADDR 0x40080000UL macro
H A DhalTSP.c2937 …IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_3_ADDR, OPENRISC_IP_3_ADDR + OPENRISC_IP_3_SIZE) || in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/
H A DregTSP.h1195 #define OPENRISC_IP_3_ADDR 0x40080000UL macro
H A DhalTSP.c2941 …IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_3_ADDR, OPENRISC_IP_3_ADDR + OPENRISC_IP_3_SIZE) || in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/
H A DregTSP.h1193 #define OPENRISC_IP_3_ADDR 0x40080000UL macro
H A DhalTSP.c2952 …IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_3_ADDR, OPENRISC_IP_3_ADDR + OPENRISC_IP_3_SIZE) || in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DregTSP.h1729 #define OPENRISC_IP_3_ADDR 0x40080000 macro
H A DhalTSP.c4346 …IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_3_ADDR, OPENRISC_IP_3_ADDR + OPENRISC_IP_3_SIZE) || in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DregTSP.h1885 #define OPENRISC_IP_3_ADDR 0x40080000UL macro
H A DhalTSP.c4765 …IsCover(phyhwaddr, phyhwaddr + u32Size, OPENRISC_IP_3_ADDR, OPENRISC_IP_3_ADDR + OPENRISC_IP_3_SIZ… in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DregTSP.h1905 #define OPENRISC_IP_3_ADDR 0x40080000UL macro
H A DhalTSP.c4728 …IsCover(phyhwaddr, phyhwaddr + u32Size, OPENRISC_IP_3_ADDR, OPENRISC_IP_3_ADDR + OPENRISC_IP_3_SIZ… in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DregTSP.h2075 #define OPENRISC_IP_3_ADDR 0x40080000UL macro
H A DhalTSP.c5095 …IsCover(phyhwaddr, phyhwaddr + u32Size, OPENRISC_IP_3_ADDR, OPENRISC_IP_3_ADDR + OPENRISC_IP_3_SIZ… in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DregTSP.h2080 #define OPENRISC_IP_3_ADDR 0x40080000UL macro
H A DhalTSP.c5420 …IsCover(phyhwaddr, phyhwaddr + u32Size, OPENRISC_IP_3_ADDR, OPENRISC_IP_3_ADDR + OPENRISC_IP_3_SIZ… in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DregTSP.h2080 #define OPENRISC_IP_3_ADDR 0x40080000UL macro
H A DhalTSP.c5437 …IsCover(phyhwaddr, phyhwaddr + u32Size, OPENRISC_IP_3_ADDR, OPENRISC_IP_3_ADDR + OPENRISC_IP_3_SIZ… in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DregTSP.h2072 #define OPENRISC_IP_3_ADDR 0x40080000UL macro
H A DhalTSP.c5493 …IsCover(phyhwaddr, phyhwaddr + u32Size, OPENRISC_IP_3_ADDR, OPENRISC_IP_3_ADDR + OPENRISC_IP_3_SIZ… in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DregTSP.h2072 #define OPENRISC_IP_3_ADDR 0x40080000UL macro
H A DhalTSP.c5454 …IsCover(phyhwaddr, phyhwaddr + u32Size, OPENRISC_IP_3_ADDR, OPENRISC_IP_3_ADDR + OPENRISC_IP_3_SIZ… in HAL_TSP_SetFwDbgMem()